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Author Topic: Saturn Takeover Mode  (Read 4357 times)
meik84
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« on: August 09, 2010, 09:06:38 AM »

One thing that I came across yesterday: The Saturn-Takeover doesn't work. Guidance sw is in CMC, V48 is set correctly, V46E is in, but the CMC doesn't deflect the error needles.
« Last Edit: August 10, 2010, 03:37:33 AM by Tschachim » Logged
Tschachim
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« Reply #1 on: August 10, 2010, 03:42:32 AM »

It's not implemented in the latest beta, but should work with the code currently in CVS. If you compile the modules by yourself and use Orbiter 2010, could you provide a scenario? Ah, and SC CONT - CMC just in case...

Cheers
Tschachim
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meik84
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« Reply #2 on: August 10, 2010, 05:41:59 AM »

Quote
SC CONT - CMC
That did it. But it's not in the checklist. Yet another speciality of Colossus Confused, the word checklists apply to Apollo 12, which had Comanche on board...
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Tschachim
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« Reply #3 on: August 10, 2010, 05:46:58 AM »

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SC CONT - CMC
That did it. But it's not in the checklist.

Well, I can speak for the Checklist MFD checklist only, and it indeed does not cover the on-orbit stuff yet.

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Tschachim
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meik84
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« Reply #4 on: October 07, 2012, 06:16:20 AM »

I guess I've found out why we've got to put SC CONT to CMC although it's not on the checklist: our 'virtual' RHC breakout switches for the CMC aren't powered when SC CONT is in SCS. This is wrong. The power path is MAIN BUS A(B) -> EPS GROUP 1 MNA (B) cb -> SCS CONTR AUTO MNA (B) cb -> ROT CONTR PWR NORMAL 1 (2)- AC/DC -> breakout switch -> channel 31 of CMC.
Additionally, when the LV GUIDANCE sw is set to CMC bit 10 of channel 30 has to be powered (i.e. to be reset -the CMC inverts the inputs from channels 30 - 33 internally). The CMC in return sets bit 9 of channel 12 to enable the demodulators of the ICDU error counters, whose outputs are provided to the IU.
See pp. 278 to 281 of CSM 104 systems handbook on that.
@tschachim: you or me? If me: where do I find that in the code?
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Tschachim
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« Reply #5 on: October 07, 2012, 03:23:50 PM »

@tschachim: you or me? If me: where do I find that in the code?

I'll take a look, thanks for pointing that out.  Happy
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meik84
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« Reply #6 on: October 07, 2012, 03:58:30 PM »

Ok. Happy
Oh, and don't forget to wire the LV GUIDANCE sw between the demodulators and the IU. I didn't notice that the switch also powers the S/C control relay in the IU, which switches between LVDC and CMC input.

Different (but related) topic: you should take a closer look at pp. 395, 396, 429 and 430 of the sys handbook (the pages were scanned in the wrong order, obviously). I can't help myself, but doesn't it show that the CMC can't fire jets when the resp. MANUAL ATTITUDE sw is in ACCEL CMD? Confused
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Tschachim
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« Reply #7 on: October 20, 2012, 04:10:24 PM »

As usual, you're right in all points.  Thumbs Up

I guess I've found out why we've got to put SC CONT to CMC although it's not on the checklist: our 'virtual' RHC breakout switches for the CMC aren't powered when SC CONT is in SCS. This is wrong.

Fixed.

Additionally, when the LV GUIDANCE sw is set to CMC bit 10 of channel 30 has to be powered (i.e. to be reset -the CMC inverts the inputs from channels 30 - 33 internally).

Done.

The CMC in return sets bit 9 of channel 12 to enable the demodulators of the ICDU error counters, whose outputs are provided to the IU.

Interestingly this is not the case, at least Colossus 249 seems to ignore ch30 bit10, ch12 bit9 is controlled by the S-IVB DAP setting. Anyway, the S-IVB now looks at ch12 bit9 and uses the error counters only if it's set, so you need to have the DAP in S-IVB mode actually to control the S-IVB.

Quote
...don't forget to wire the LV GUIDANCE sw between the demodulators and the IU. I didn't notice that the switch also powers the S/C control relay in the IU, which switches between LVDC and CMC input.

This was already the case before, i.e. with LV GUIDANCE - IU the IU controls the S-IVB entirely, the CMC is ignored. With LV GUIDANCE - CMC, the error counters are used when ch12 bit9 is set. If the bit is not set (or if there's not input from the error counters, of course), it's attitude hold effectively.

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I can't help myself, but doesn't it show that the CMC can't fire jets when the resp. MANUAL ATTITUDE sw is in ACCEL CMD?

No need to read the schematics, it's stated in plain English in the AOH, see screenshot, and I overlooked it all the years...  Ashamed
I fixed it, I hope I got it right, it was a bit tricky...

All changes are in CVS.

Cheers
Tschachim


* accelcmd.PNG (235.1 KB, 1071x840 - viewed 384 times.)
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meik84
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« Reply #8 on: October 20, 2012, 05:18:08 PM »

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Interestingly this is not the case, at least Colossus 249 seems to ignore ch30 bit10, ch12 bit9 is controlled by the S-IVB DAP setting.
I think you can't read AGC code... Wink
Anyway, tempt fate and Artemis wants to have it.
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I fixed it, I hope I got it right, it was a bit tricky...
Just imagine that in reality this logic was made with discrete components. At least two transistors for a AND-gatter, three for a NAND... Happy soldering! Shocked
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meik84
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« Reply #9 on: October 30, 2012, 01:00:57 PM »

Only related indirectly to SIVB-takeover, but has something to do with it: do we use bit 6 of chan 12 for enabling the ICDU error counters? The thing is that when the CMC drives the error needles during roll/pitch program this bit is set (i.e. the error counters are enabled); it is reset at 163.84 secs after liftoff, which disables the error counters and sets them to 0. Obviously our error counters aren't set to 0 when this bit is reset.
Just came along that little thingy during one of my many testflights for LVDC when I wondered why the CMC doesn't drive the needles to 0 when pitch polynominal is over.
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Tschachim
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« Reply #10 on: October 31, 2012, 07:26:53 AM »

do we use bit 6 of chan 12 for enabling the ICDU error counters?

Yes.

Obviously our error counters aren't set to 0 when this bit is reset.

They are set to 0 when this bit is set (which is mandatory to have a proper initialization e.g. in case something was turned off before). I'm not sure if they are set 0 when this bit is reset, do you have a source for that?

If you want to set them to 0 if this bit is reset, look for CSMcomputer::ProcessIMUCDUErrorCount in CSMcomputer.cpp and add the red lines:

switch(channel){
case 012:
   // Reset FDAI
   if (val12.Bits.EnableIMUCDUErrorCounters) {
      if (sat->gdc.fdai_err_ena == 0) {
         // sprintf(oapiDebugString(),"FDAI: RESET");
         sat->gdc.fdai_err_x = 0;
         sat->gdc.fdai_err_y = 0;
         sat->gdc.fdai_err_z = 0;
         sat->gdc.fdai_err_ena = 1;
      }
   } else {
      if (sat->gdc.fdai_err_ena == 1) {
         // sprintf(oapiDebugString(),"FDAI: RESET");
         sat->gdc.fdai_err_x = 0;
         sat->gdc.fdai_err_y = 0;
         sat->gdc.fdai_err_z = 0;
      }

      sat->gdc.fdai_err_ena = 0;
   }
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meik84
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« Reply #11 on: October 31, 2012, 08:21:02 AM »

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I'm not sure if they are set 0 when this bit is reset, do you have a source for that?
Si. CSM 104 sys handbook, p. 280; unfortunately the page has been scanned badly and the bit/channel label has been cut away except for the "6", but it's clearly stated: "ZEROES CNTR WHEN NOT", i.e. when this bit is 0, the counters are kept at 0 whatever you feed to them. Only when bit 6 is 1 the counters can output anything different from 0. Seems like some sort of gate logic.
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Tschachim
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« Reply #12 on: October 31, 2012, 11:57:11 AM »

OK, thanks for the info. Do you want to insert the red lines on your side and see if it's better during launch? I don't do launch tests at the moment...

Cheers
Tschachim
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meik84
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« Reply #13 on: October 31, 2012, 01:03:21 PM »

I have already. Works. Thumbs Up
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Tschachim
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« Reply #14 on: November 01, 2012, 09:16:12 AM »

Great! Do you want me to put that to CVS or do you do it together with the LVDC++?
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