.TITLE FIS SIMULATOR .IDENT /V1.01/ .ENABL LC .DSABL GBL .NLIST TOC,SYM,CND ; Author: C J Doran ; Sira Ltd., South Hill, Chislehurst, Kent, BR7 5EH, England ;+ ; This module simulates the floating instruction set (FIS) using ; a floating-point processor (FPP). ; Some special procedures are required:- ; 1. Illegal instruction and FIS exception traps must be .IIF DF RSX11M,; set by the SVTK$ directive. .IIF DF RT11,; set by .TRPSET, & in addr 244 respectively. ; 2. FPP status must be set to 3000, and never changed. .IF DF RSX11M ; 3. FPP interrupts to location FPERR must be enabled ; (SFPA$ FPERR). .ENDC ; ; For example initialisation code, see the test program included. ; ; Assemble as: ; ; >MAC FISSIM=FISSIM ;- ; Define P11.34 or P11.45 if either PDP11/34a or PDP11/45 in use. ; Leave both undefined on any other processor. P11.34=0 ; If PDP 11/34 ;P11.45=0 ; If PDP 11/45 ; Define ONE of RT11 or RSX11M according to the system in use RSX11M=0 ;RT11=0 ; Define TEST to assemble the test program. TEST=0 .PSECT FISDAT,D,RW,CON .IIF DF RSX11M, .MCALL ASTX$S,GTSK$S .IIF DF RT11, .MCALL .SFPA ERRCC: .BYTE ^B1011,^B0000,^B0010,^B1010 ; Error return CCs ; Save registers area .IRPC REG,<01234567> SAVER'REG: .BLKW 1 .ENDR .IIF DF RSX11M, .BLKW 8. ; Extra 8 words for GTSK$ .PSECT FISSIM,I,RO,CON ILLINS:: ; Trap to 10 -- illegal instruction .IIF DF RT11, BCC BREAK ; CC => odd addr MOV %5,SAVER5 ; Save a work register MOV @SP,%5 ; Get return address CMP -(%5),#FADD ; Address-2 is failing instr BLO 10$ ; If < FADD, don't simulate CMP @%5,#FDIV!7 ; Highest code is FDIV PC BLOS FISSIM ; FIS instruction if in range 10$: MOV SAVER5,%5 ; Else restore %5 BR BREAK ; and crash ; Must find the register from the instruction code to fetch ; operands and then find the instruction itself. F0=%0 F1=%1 FISSIM::.IRPC REG,<01234> ; Save registers (%5 done) MOV %'REG,SAVER'REG .ENDR .IIF DF RT11, .SFPA #FPERR ; Set FPP exception trap MOV (SP)+,SAVER7 ; Save PC (register could be SP) MOV (SP)+,%0 ; and PS in %0 MOV SP,SAVER6 ; Complete the set with SP MOV @%5,%5 ; Get full instruction code MOV %5,%4 ; making a copy BIC #^C7,%5 ; Get register ASL %5 ; Shift for ptr to saved regs ADD #SAVER0,%5 ; Point to appropriate register LDF @(%5)+,F0 ; Load first operand ADD #4,-(%5) ; Update register LDF @(%5)+,F1 ; Fetch second operand BIC #^C30,%4 ; Select the function bits only ASR %4 ; Shift once and add to PC ADD %4,PC ; to execute appropriate instr ADDF F0,F1 ; 7500R is add BR 10$ ; OK if instruction returns SUBF F0,F1 ; 7501R is subtract BR 10$ MULF F0,F1 ; 7502R is multiply BR 10$ DIVF F0,F1 ; 7503R is divide 10$: ; All OK, put CC bits into %4. .IF DF P11.34 ; If PDP 11/34, can use MFPS CFCC ; Get flags MFPS %4 ; to %4 .IFF ; If not 34, do it the hard way OK: STFPS %4 ; Get CC bits BIC #^C^B1100,%4 ; N and Z only .ENDC BR RET ; Return ; Trap to here if an error occurs. Set correct bits according to ; FPP status pushed onto the stack by the system. FPERR:: TST (SP)+ ; Don't need FEA MOV (SP)+,%4 ; Get FEC ASR %4 ; as a byte pointer MOVB ERRCC-2(%4),%4 ; Fetch return code CLRF F1 ; Will return 0.0 .IF DF RSX11M MOV #RET,2(SP) ; Set branch address ASTX$S ; For return from AST .ENDC RET: STF F1,@-(%5) ; Store result BIC #^B1111,%0 ; Delete CCs from old PS BIS %4,%0 ; Put in new ones MOV SAVER6,SP ; Restore SP in case FXXX SP MOV %0,-(SP) ; Push PS MOV SAVER7,-(SP) ; and return address .IRPC REG,<045> ; Restore altered registers MOV SAVER'REG,%'REG .ENDR BIT #^B10,2(SP) ; V bit set in PS => error BEQ EXIT ; OK if not set MOV 2(SP),-(SP) ; Error! Stack PS again .IF DF RSX11M GTSK$S #SAVER0 ; Get task parameters CMP SAVER0+G.TSVL,#8. ; Any FIS exception trap? BLO 10$ ; No, error is fatal MOV SAVER0+G.TSVA,-(SP) ; Yes, get trap vector addr ADD #14.,@SP ; @G.TSVA+14. = FIS exception ad MOV @(SP)+,-(SP) ; Put exception address on stack .ENDC .IIF DF RT11, MOV @#244,-(SP) ; and user trap address BNE EXIT ; OK if exception address given TST (SP)+ ; Else purge exception addr 10$: TST (SP)+ ; and PS BREAK: BPT ; Fatal -- break to ODT or crash EXIT: RTI ; Restore PS, return somewhere .IF DF TEST .PAGE .SBTTL TEST PROGRAM .PSECT .IIF DF RSX11M, .MCALL SVTK$C,EXIT$S,SFPA$S .IIF DF RT11, .MCALL .TRPSET,.EXIT START: LDFPS #3000 ; Enable FPP interrupts .IF DF RSX11M SVTK$C VECTBL,8. ; Set traps SFPA$S #FPERR ; Set FPP trap .ENDC .IF DF RT11 .TRPSET #ILLINS ; Set ill ins/odd addr trap MOV #FISTRP,@#244 ; Set FIS trap .ENDC MOV #PLUS,%0 FADD %0 MOV #MINUS,%1 FSUB %1 MOV #MULPLY,%2 FMUL %2 MOV #DIVIDE,%3 FDIV %3 MOV #PLUSOV,%4 FADD %4 MOV #MULOV,%5 FMUL %5 MOV #MULUN,%5 FMUL %5 LDF #^F1,F0 ; Try stacked operands STF F0,-(SP) CLRF -(SP) ; 1/0 FDIV SP CMP (SP)+,(SP)+ ; Purge stack FSUB PC ; PC is valid, but silly .FLT2 0 .FLT2 0 ; Returning to this HALT! .IIF DF RSX11M, EXIT$S .IIF DF RT11, .EXIT FISTRP: NOP ; Dummy FIS exception trap RTI .IF DF P11.45 VECTBL:: .WORD ILLINS,0,0,0,0,0,0,FISTRP ; TRAP VECTOR .IFF VECTBL:: .WORD 0,0,0,0,ILLINS,0,0,FISTRP ; TRAP VECTOR .ENDC ; Sums PLUS: .FLT2 4,3,7 ; 3+4=7 MINUS: .FLT2 6,5,-1 ; 5-6=-1 DIVIDE: .FLT2 -6,-18,3 ; (-18)/(-6)=+3 MULPLY: .FLT2 6,0.5,3 ; 0.5*6=3 PLUSOV: .FLT2 1.5E38,1.5E38,0 ; 1.5E38+1.5E38=OVERFLOW MULOV: .FLT2 1E20,1E20,0 ; 1E20*1E20=OVERFLOW MULUN: .FLT2 1E-20,1E-20,0 ; 1E-20*1E-20=UNDERFLOW .ENDC .IIF DF TEST, .END START .IIF NDF TEST, .END