Subject: Follow to my first comment

From: [email-masked] (JRW)
Date: Wed, 5 May 1993 19:36:54 GMT

This reply is in response to comments to my first posting.  Actually I was 
delighted to see that some of you still care about the PDP-8.  If you are 
under thirty, you probably have no interest in my comments and probably 
wonder what is a PDP-8.?

No I didn't get the PDP-8 mneumonics from a book, but from memory.  

I do have many fond memories of working with PDP-8s from a 4k 8/s to a 32k  
8/e with hard disk.  I also remember feeding paper tape to a teletype and 
waiting to see if the checksum was zero, assembling code in my head and 
toggling it in, watching a program execute by observing the light patterns (
signature analysis), etc.  

I still marvel at the efficient software that could run in 4k.  Even a 
Fortran complier but you all probably know this too.

With the low price of PCs, it was surprising to me that any one would still 
want to contend with the PDP-8 and the extra labor involved in writing code 
for it.

I have always wondered if DEC had gone with 8 bit words instead of 12 bit 
words, would the PDP-8 continued to evolve much as the 8080 has evolved to 
the 80486?

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From: jones@pyrite (Douglas W. Jones,201H MLH,3193350740,3193382879)
Date: Wed, 5 May 1993 20:25:35 GMT

>From article <[email-masked]>,
by [email-masked] (JRW):
> 
> I have always wondered if DEC had gone with 8 bit words instead of 12
> bit words, would the PDP-8 continued to evolve much as the 8080 has
> evolved to the 80486?

The evolution of the PDP-8 certainly parallels some of the 8086 evolutionary
trends.  Consider:

  Address space problems -- the PDP-8 memory field switching mechanism
    (used to break the 4k limit) is certainly less elegant than the general
    segmented memory system used on the 8086 to break the 64k limit of
    the 8080.

    On the other hand, the PDP-8's field switching mechanism beats the
    pants off of the bank switching schemes used on the IBM PC to address
    beyond 640K.

  Word size problems -- the PDP-8/E EAE extends the instruction set of
    the basic PDP-8 in a way that adds "register irregularity" that is
    just as bad as the irregularity of the 8080 that was carried over
    into the 8086 -- that is, you've got one accumulator for single
    precision, a different accumulator for double precision, and a strange
    problem of shoving operands back and forth so you can get work done.

On the other hand, the 8086 is pipelined (to a surprising extent), but
I've never seen a pipelined PDP-8!
					Doug Jones
					[email-masked]

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From: [email-masked] (Charles Lasner)
Date: Wed, 5 May 1993 22:13:53 GMT

>I've never seen a pipelined PDP-8!

What do you expect when the company has an almost zero hardware budget, and
all of the effort is put into adding frills to the -11?

How about someone coming up with a paper design for a pipe-lined -8 CPU
using modern logic to implement it, etc.

Incidentally, others suggested an 8086-like way to (admittedly incompatibly)
extend the -8 address space, but DEC never did it.  The windowing of memory
could be done quite straightforwardly, but we're sort-of stuck with doing
our own memory management in the program.  Of course, that does allow us
to use up to 32K in any -8, 128K in a KT8A machine, and 512K in an MEC8
machine.  (Note that 512K x 12 = 768K x 8, whereas PC's have problems beyond
640K x 8 due to IBM's design limitations.)

cjl

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From: [email-masked]
Date: 5 May 93 22:22:59 MDT

> using modern logic to implement it, etc.

Actually, I'm more interested in stuff like programming one into a big
Xilinx. The 4005 series should have more than enough space. That's right,
we are entering the age where you can roll your own CPU...

I think the PDP-5 might work better as a Xilinx machine. Yes, putting the
PC in location zero is a bitch, but it lets you make a nice clean break
between the CPU and everything else. The interrupt controller, for example,
could be simply a DMA device; it copies location zero to location two and
then stuffs a one in location zero. Further, a PDP-5 could be optimized to
come within the speed of a PDP-8; after all, it only _really_ has to store
the PC when it gives up the bus to a DMA device...

Roger "I'm 30 and the PDP-5 will be soon" Ivie
[email-masked]

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From: [email-masked]
Date: 5 May 93 22:19:19 MDT

> I've never seen a pipelined PDP-8!

Given the number of memory references that a PDP-8 instruction might have
to do (can you say ISZ I Z 10? I knew you could), I don't think you can
get very far pipelining a PDP-8.

Roger Ivie
[email-masked]

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From: [email-masked] (Charles Lasner)
Date: Thu, 6 May 1993 21:12:33 GMT

>get very far pipelining a PDP-8.

True, but not a statistically likely instruction.  ISZ I {not 10-17} ain't
that more likely either.  ISZ non-indirect is somewhat more likely of course.

The bulk of the stuff is TAD, followed close by DCA, then JMP then JMS.  AND
and IOT's are fairly rare, except for non-interrupt programming with the
skip; jmp .-1 stuff, etc.

cjl

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From: [email-masked] (Dave McGuire)
Date: 7 May 1993 21:41:09 GMT

JRW ([email-masked]) wrote:
: This reply is in response to comments to my first posting.  Actually I was 
: delighted to see that some of you still care about the PDP-8.  If you are 
: under thirty, you probably have no interest in my comments and probably 
: wonder what is a PDP-8.?

  Hmmm... I'm quite a bit below thirty...I have several 8's and LOVE
THEM ALL... It started out as simple curiosity, then became somewhat
of an obsession.  It's toned down a bit now, but I still LOVE those
8's...They're actually quite quick when you come right down to it.
I've got a 28mip SPARC on my desk and computer power to spare in the
computer room, but the 8 has never dissapointed me with its
performance, I must say.  They're a pleasure to run, even if they're
not really suitable for practical work any more.

: With the low price of PCs, it was surprising to me that any one would still 
: want to contend with the PDP-8 and the extra labor involved in writing code 
: for it.

  Low price, low performance, low quality of design, low reliability,
low intelligence of architecture, low lack of kludges just to get more
than one stupid program at a time running on the damn thing, need I
continue?

      -Dave McGuire
       Systems Programmer
       Digital Express Group, Incorporated
       [email-masked]

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From: [email-masked] (Charles Lasner)
Date: Sat, 8 May 1993 04:10:19 GMT

>than one stupid program at a time running on the damn thing, need I

While we all know that MIPS is "Meaningless instructions per second" or 
something worse, the -8's fastest instruction is far from meaningless,
since a NOP takes the same time as the most complicated group 1 operate
instruction (or group 2 for that matter; if EAE is implemented, group 3
does take longer, such as Multiply or Divide, etc.)

So, the MIPS is not based on some farfetched fast NOP, but on how fast it
can execute something like

	CLA CLL CML RTL

Which is to clear the accumulator, clear the link, then complement the link
and then rotate the whole 13-bit quantity two places left leaving the constant
0002 in the accumulator, and the link clear; this is hardly a "meaningless"
instruction, but it none-the-less takes the same time as the fastest NOP.

The -8 is "frozen" in time because its CPU boards were all designed prior to
1971.  Even the 8/a's fastest version is just the highest rev kk8f CPU boards
that are for the earliest late'70-early'70 8/e.

Thus, unlike all of the other highly funded DEC product lines, the -8 never
had the ability to take advantage of faster logic, and is actually competing
with machines that have lots more MIPS, etc.  The -8 is actually quite a
bit under 1 MIPS by any definition, although because of just what a MIPS
might be, I would want to boost the number up somewhat.  (And this is only
to favor the newer designs, since they ain't so much more powerful as the
MIPS ratio would indicate, since you are comparing PDP-8 OPR instructions to
contrived NOP speeds on CPU's where the fast NOP isn't as representative.)

However, the -8 has some other "unfair" advantages:

Statistically, most subroutine calls on most architectures are really performed
only for the basic transfer of control reason, the fundamental notion of just
what a subroutine means.  But most architectures have become muddied up with
unrelated issues such as stack operations, etc., so there isn't even any such
thing as a simple subroutine call.  In fact, most code gets written in 
languages that wouldn't even be able to take advantage of a subroutine
linkage mechanism without a stack even if available.  (A side note: notice that
the PDP-10 supports both PDP-8-JMS-like operations, as well as PUSHJ/POPJ
stack-oriented calls at the user's option.)

Thus, while clearly there are cases where the overhead is required, the
majority of cases are overhead-ridden with cycles begging to be trimmed away,
but the hardware is incapable of doing it.  (There is usually more overhead
trying to "fake" a non-stacked subroutine call than to just let it do it the
usual way.)  The PDP-8 doesn't have the overhead-ridden hardware available
(the 6120 *does* have it BTW) and can only do the simple JMS subroutine call.

So, there is a statistical advantage of implementing any reasonable algorithm
that involves nested subroutines on the -8 or similar machines as compared to
many "modern" architectures, etc.  The -8 will just run much faster, MIPS for
MIPS, etc.  (Admittedly, a lot of machines make up for this by brute force,
by having more MIPS available, but that's besides the point, since a high-MIPS
-8 would match them on the MIPS ratio if the proper hardware was used to
implement an -8 CPU and memory, etc.)

Another related "advantage" the -8 has is that the code often implemented on
the -8 includes the co-routine mechanism, a data structure virtually ignored
in most architectures.  (Due to the usual overhead, most architectures can't
have a coroutine structure without incurring more overhead than could be
saved, thus they avoid it!)

While not a PDP-8-exclusive feature, the -8 implements it in a low-overhead
manner.  Consider two different ways (on the -8) to implement the same
algorithm.  The first is easily translated efficiently to any other machine
and the second may be more trouble that it's worth elsewhere:

/	SUBROUTINE TO UNPACK A CHARACTER STRING BY HALFWORDS

GETONE,	.-.			/MAIN ENTRY
	NL4000			/SET FLIP BIT
	TAD	WHICH		/GET WHICH HALF INDICATOR; ALSO SETS LINK!
	DCA	WHICH		/STORE IT BACK
	TAD I	PTR		/GET A PAIR
	SZL			/WHICH ONE IS ON THE RIGHT CURRENTLY
	BSW			/THE WRONG ONE, SO REVERSE THEM
	SNL			/ARE WE DONE WITH THIS WORD?
	ISZ	PTR		/YES, BUMP TO THE NEXT ONE
	AND	(77)		/ISOLATE THE HALF WE JUST GOT
	JMP I	GETONE		/RETURN TO CALLER

Notice that we need to have the initialized temporary WHICH set to 0000 to
get the left-half first, and we then get the right half before advancing to
the next word.  This sort of thing or a simple variant of it translates well
to other machines.

Now consider the co-routine alternative method:

/	SUBROUTINE TO UNPACK A CHARACTER STRING BY HALFWORDS

GETONE,	.-.			/ROUTINE ENTRY
	JMP I	GETOUT		/GO WHERE YOU OUGHT TO GO

/	EXIT ROUTINE FOR GETONE

GETOUT,	GET1			/COROUTINE EXIT ROUTINE; INITIALIZED FIRST TIME
	AND	(77)		/MASK OF TO ONLY DESIRED BITS
	JMP I	GETONE		/RETURN TO MAIN CALLER

GET1,	TAD I	PTR		/GET A PAIR
	BSW			/WANT LEFT-HALF FIRST
	JMS	GETOUT		/GIVE IT TO THEM; COMES BACK LATER
	TAD I	PTR		/GET THE PAIR AGAIN
	JMS	GETOUT		/GIVE THEM RIGHT-HALF NOW
	ISZ	PTR		/BUMP TO NEXT PAIR
	JMP	GET1		/GO DO IT AGAIN

In this version, the main caller is always directed to the proper portion
of the inner driving code as required.  Thus, each call sets up the *next*
call if required.  The GETOUT contents must be initialized the first time
and there is no SWITCH variable required.

This simple structure doesn't change in form, even if the program requirements
grow, such as a more complicated data structure form requiring additional
flags/switches in the former implementation, since the flow control form
is a constant regardless of complexity.  The simple JMS instruction makes
the whole thing viable with lowest possible overhead since it's being used
for flow control, not merely as a subroutine.

>From the vantage point of the inner driving loop, the main caller is a
"subroutine" as well as the usual vantage point "inverse" to that one, thus
the whole thing is known as a coroutine because there is no clear 
subordination, etc.

In interrupt handling, the same structure can be applied to the transfer
of control between the foreground and the background, etc.  To the interrupt
handler, the main program is the "subroutine" etc.

So, many -8 applications are unfairly efficient, as compared to more "modern"
machines :-).  (Imagine an -8 built with enough MIPS to "compete".)

cjl