Subject: When is PC incremented?

From: [email-masked] (VENESS J)
Date: Sun, 7 Nov 93 01:15:23 GMT

Hello (-;

This is my first posting to this group so allow me to introduce myself.  My
name is John Veness, and as my final year BSc Computer Science project here
at Royal Holloway, University of London, I'm writing a Structural Simulator
of a PDP-8 with Graphical User Interface (so it says 'ere ;).  Hi to my tutor, 
Adrian Johnstone, if he's reading btw!  I'm writing it in C, using Motif.

Now my question.  As I'm doing a *structural* simulator, I want it to be as
close to the actual -8 hardware as possible.  I've got Intro to Programming
and a copy of user manuals (PDP-8/L and /A) and I've read the FAQs and
WHAT-IS-A-PDP8 and I've noticed an inconsistency in the documentation as to
when exactly (ie which major state - Fetch, Defer, or Execute) the Program
Counter is incremented.  In Intro to Programming, the PC is said to *always*
contain the address of the next instruction to be executed (my emphasis).  In
the PDP-8/L users manual it says that after the instruction is transferred
from the address pointed to by the PC, and after the opcode is transferred
to the IR, the PC is incremented by one.

So these two both agree that the PC is incremented practically straightaway
after used to fetch the instruction currently being executed.  The thing
that struck me was what about Memory Reference Instructions which use
addresses on the current page?  Specifically what about an MRI instruction
on the last word (offset 0177) on a page?  The current page is defined in the
PDP-8/A manual as the page containing the instruction being *executed*, as
determined by bits 0-4 of the PC (my emphasis - bit's 0-4 are the high bits).
If the PC is always pointing to the *next* instruction to be executed, then 
this contradicts that, in the case where the instruction is at the end of a
page boundary (as bits 0-4 of the PC will be one greater than they should).

Also, in the PDP-8/L manual, the documentation of JMS says that the contents
of the PC are written into the address designated by the instruction, and then
that address is loaded into the PC.  Considering that JMS stores the address
one after the JMS instruction into the address given in the instruction, this
says that PC is incremented before it is stored there.  But saying that the PC
is then set to that address, implies that the PC is incremented *after* that,
as control passes to the instruction *after* the address designated by the
instruction.

I hope I've made my confusion clear!  Can any1 tell me what the correct
situation is?

		John 'Pelago' Veness

---

From: jones@pyrite (Douglas W. Jones,201H MLH,3193350740,3193382879)
Date: Mon, 8 Nov 1993 00:28:46 GMT

>From article <[email-masked]>,
by [email-masked] (VENESS J):

> Now my question.  ...

Looking at Figure 3.8 of the PDP-8/E Processor Maintenance Manual, in TS1,
the PC is incremented, but MA (the memory address register) holds the
value of PC prior to increment.  Then, TS2 and TS3 do things, and
finally, in TS4, the MODIFY CPMA stuff happens, during which bits of
MA may be transferred to CPMA to build the operand address.  Enough?

					Doug Jones
					[email-masked]