Subject: Re: Group 3 OPR instructions

From: [email-masked] (Bob Supnik)
Date: 30 NOV 93 21:39:03

In article <[email-masked]>, [email-masked] (John E. Veness) writes...
> [text deleted]
>I wish to add the group 3 OPRs, but I don't really have documentation on them.
> [text deleted]
>Anyway, I don't have any details of the EAE instructions, as the 6100

I have them written, as part of a simulator package.  Send email, and I'll
send you the CPU source if you want.  Note that they are NOT debugged.

Bob Supnik	>[email-masked]
		>All opinions expressed are those of a hardline microcoder
		>and do not reflect those of Digital Equipment Corporation

---

From: [email-masked] (Megan)
Date: Wed, 1 Dec 1993 21:11:40 GMT

[email-masked] (John E. Veness) writes:

>Anyway, my question this time is a very simple one.  I've so far
>simulated all the MRI instructions, the group 1 OPR instructions, and
>the group 2 OPR instructions.  I wish to add the group 3 OPRs, but I
>don't really have documentation on them.  I have Intro to Programming,
>and a Intersil 6100 book, and they don't really help.  The 6100 seems
>to have three instructions in group 3, CLA, MQL, and MQA (working out
>how to do the combination SWP of MQL and MQA was just a bit difficult
>- well, a bit more than the two separately).

Well, there is bit 06, SCA, which logical ors the step counter (SC)
with the AC.

Bits <08:10> are a three-bit field which encode the EAE operation to
perform.
	0 = no operation
	1 = SCL (load's step counter from contents of address PC+1
	2 = MUY (multiply MQ by contents of address PC+1, results
		into AC (high-order 12 bits) and MQ (low-order 12
		bits)
	3 = DVI (divide combined AC/MQ by contents of address PC+1,
		quotient in AC, remainder in MQ, if I remember
		correctly)
	4 = NMI (normalize, shifts combined AC/MQ left until AC0
		and AC1 do not match OR AC/MQ = 06000000, step
		counter (SC) gets count of shift.  AC0 shifts to
		L, bits shifted out of L are lost)
	5 = SHL (Shift left combined AC/MQ by contents of PC+1
		incremented by one.  AC0 shifts to L, L shifts to
		bit bucket)
	6 = ASR (Arithmetic shift right combined AC/MQ by contents of
		PC+1 incremented by one.  AC0 at start of instruction
		specifies contents of L at end of instruction as well
		as bits shifted into AC0, shift out of MQ11 is lost)
	7 = LSR (Logical shift right combined AC/MQ by contents of
		PC+1 incremented by one.  Zeros shift into AC0, MQ11
		shifts to bit-bucket).

This is what I understand so far.  It is 'mode A' operation.  Apparently
mode B operation changes where the shift count for some operations come
from.  I think it means that the contents of PC+1 is the address of
the location from which you get the count.

This also means that there are additional instructions (SWAB - switch
mode from A to B, and SWBA - switch mode from B to A).

There are also some double precision instructions, but I have yet
to read up on them (the rest of the above was from memory).

					Megan Gentry
					Former RT-11 Developer

---

From: [email-masked] (Charles Lasner)
Date: 13 Dec 1993 01:04:23 GMT

>the location from which you get the count.

Not quite right.  In Mode A, the next word is the count-1, thus SHL;0 does one
shift.  In Mode B, the next word is the exact count, thus SHL;0 is a NOP.  All
counts are always the same for all count-type iunstructions.  In Mode A, the
arg for the MUY or DVI follows in-line.  In Mode B, a pointer to the arg
follows, and the DF thus matters.  In fact, if the MUY instruction is placed
into location 0007-0016, the Mode B version auto-indexs!

>mode from A to B, and SWBA - switch mode from B to A).

Yes.  SWAB is a hack - it avoids a bug of all prior EAE implementations:

If the AC or MQ is non-zero, then CLA [MQL if necessary] NMI hangs the
hardware up in an infinite loop.  This is because the special-case
check for NMI-not-necessary is done before the check for AC,MQ will
become 0000,0000.  To substantially avoid this, SWAB is actually
CLA NMI!

>to read up on them (the rest of the above was from memory).

Double-add, store, increment, check-if-zero, clear-and-store-zero,complement
are all present.  The ones that need address operands take the pointer from
the next word.

There is an instruction (SAM) to subtract the AC from the MQ and store the
result's status into the "greater-than" flag.  Note that 6006 is skip on
the GTF set, and it's part of the get-flags/restore-flags sequence.  Also,
in Mode B, the low-order bit isn't lost on a right shift; it winds up in the
GTF.

cjl