Subject: Re: EAE SAM instruction

From: [email-masked] (Bob Supnik)
Date: 1 Mar 1994 19:05:27 GMT

This is from the PDP8/E Maintenance Manual, Volume 2, Part 1, Extended
Arithmetic Element

(Description of SAM)

'The "Greater Than" signal is derived as follows:

	a. If the MQ and the old AC are of different signs, the MQ is greater
	   than the AC if the MQ is positive.  The MQ is less than the AC if
	   the MQ is negative.

	b. If the MQ and the old AC are of the same sign, the MQ is greater
	   than (or equal to) the old AC if the output of the most-significant
	   bit of the adder is positive.  Otherwise, the MQ is less than the
	   AC.

Logic at the input of the gT flag computes the "Greater Than" signal.'

So:

L = (unsigned) AC <= (unsigned) MQ
gtf = (signed) AC <= (signed) MQ

SAM with AC = 1, MQ = 2: L = 1, gtf = 1
SAM with AC = 3, MQ = 2: L = 0, gtf = 0
SAM with AC = 4001, MQ = 2: L = 0, gtf = 1
SAM with AC = 2, MQ = 4001: L = 1, gtf = 0
 
--
Bob Supnik      >[email-masked]
                >All opinions expressed are those of a hardline microcoder
                >and do not reflect those of Digital Equipment Corporation

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From: [email-masked] (Charles Lasner)
Date: 2 Mar 1994 16:19:26 GMT

In article <[email-masked]>,
>SAM with AC = 2, MQ = 4001: L = 1, gtf = 0

It works as Bob describes it; I checked it out on my machine with KE8E.

I apologize for my mistatement in an earlier post on the subject.  What I
meant to say was that the greater-than flag itself isn't part of EAE.
(Not really very useful without it though!  You can load it with RTF,
retrieve it with GTF, and skip on it with SGT, but not much else.)

Another issue surfaces from this thread:

Some people were attempting to apply un-pdp-8-like arguments to explain
how it ought to work.  The reasoning stems from how *other* machines do
it.  Curiously enough, SAM works more like other machines, but not
because the rest of the -8 architecture does it that way.

The specific point is that the -8 does not set the link ever as a result
of any operation except the explicit CLL.  This isn't a problem because
you can micro-code in a CLL or even CLL CML if you need it preset before
some operation.  But in general, you are looking for a link flip or not,
as opposed to it being set as some sort of "condition code".

OK, another related question:  what is the behavior of the link in the
double-precision operations of mode B EAE?

cjl

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From: [email-masked] (Bob Supnik)
Date: 2 MAR 94 19:33:58

In article <[email-masked]>, [email-masked] (Charles Lasner) writes...
> [text deleted]

Working from the EAE maintenance manual.

1. DCM... "The KE8-E disables normal Link gatting and places CARRY OUT L
   from the adders onto the LINK DATA L line of the OMNIBUS.  The Link, AC,
   and MQ are loaded at the conclusin of each step."  In short,

   1.1  Swap AC and MQ (because MQA!MQL must be microprogrammed with this
	instruction; if not included, omit this step)
   1.2	L'AC = AC (formerly MQ) ^ 07777 + 1, the link is unconditionally
	loaded per the above
   1.3	Swap AC and MQ again
   1.4	L'AC = AC (restored) ^ 07777 + carry in = Link from step 1.2,
	the link is unconditionally loaded per the above

   Net effect: if AC'MQ = 0000 0000, L = 1 else L = 0

2. DPIC.  Essentially the same as DCM, except the input to the adder
   in steps 1.2 and 1.4 are not complemented first.

   Net effect: if AC'MQ = 7777 7777, L = 1 else L = 0

3. DAD.  A flow with many interesting side affects.

   3.1 "During TS3 of the FETCH cycle, ADLK DIS is grounded, enabling the
	OMNIBUS LINK DATA and LINK LOAD inputs... since no data was placed
	on LINK DATA, the Link is cleared."  L = 0
   3.2	SKIP is asserted, PC = PC + 1
   3.3	EN0, CARRY IN, and F D SET are asserted.  This causes MA (which
	pointed at the instruction word) to be incremented, and the
	location now addressed TREATED AS A DEFERRED OPERAND.  That it,
	it is fetched from memory and used as the ADDRESS of the operand.
	One consequence of this is that if the second word of the
	instruction is in locations 0010-0017, it is AUTOINCREMENTED:
	MA = MA + 1;
	if ((MA & 07770) = 00010) M[MA] = M[MA] + 1;
	MA = M[MA];
   3.4	The memory data and MQ are added and the results propagated
	to the Link and AC.  At the same time, the AC is moved to the MQ.
	Because the Link is cleared, this in effect unconditionally loads
	the Link with the carry:
	MQ = AC; L'AC = M[MA] + old MQ + Link (0 due to step 3.1);
   3.5	MA is now incremented to point to the next word, and the
	operation is repeated:
	MA = MA + 1;
	MQ = AC (low order result of add from step 3.4);
	L'AC = M[MA] + old MQ (original AC) + Link (carry out from 3.4)
	
   Net effect:  L'AC'MQ = (AC'MQ) + (M[MA+1]'M[MA]);

4. DST.  The Link is unchanged.  DST shares with DAD the odd use of
   DEFER state (so do MUY and DVI in mode B).

"It's just this little chromium switch over here..."

Bob Supnik	>[email-masked]

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From: [email-masked] (Johnny Billquist)
Date: 3 Mar 1994 15:59:02 +0100

>It works as Bob describes it; I checked it out on my machine with KE8E.

Interesting. Then it seems as the link is set if there isn't a
borrow. Could this mean that they start out by setting the link,
and then use Link + MQ as a 13-bit number which they substract
AC from?
Thereby being sure that the substract never really overflows.
Hmmm, sounds like a nice way to do it anyway.

>as opposed to it being set as some sort of "condition code".

Yes, that is the fact in the normal instructions, but this was the EAE.
And (I assume you a referring to my reasonings) I didn't really take
it from how other machines work, but from how hardware work. (In my
reasonings.)
I then, in another posting, made a comparision with how other
machines work, so people who might think things are strange in the
8, because of the names of things, might get a grasp.

>double-precision operations of mode B EAE?

Just like the SAM. Link indicates overflow. Clear if no overflow, set
if there is. So, no toggle there. (Only instruction which might affect
Link is DAD, DPIC and DCM.)

	Johnny
-- 
Johnny Billquist                  || "I'm on a bus
CS student at Uppsala University  ||  on a psychedelic trip
email: [email-masked]       ||  Reading murder books
pdp is alive!                     ||  tryin' to stay hip" - B. Idol

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From: [email-masked] (Charles Lasner)
Date: 4 Mar 1994 06:22:23 GMT

In article <[email-masked]>,

>   Net effect: if AC'MQ = 0000 0000, L = 1 else L = 0
So, the L is loaded, not flipped while CIA would merely flip the L.

>   Net effect: if AC'MQ = 7777 7777, L = 1 else L = 0
So, again the L is loaded while IAC would flip the L.

>   Net effect:  L'AC'MQ = (AC'MQ) + (M[MA+1]'M[MA]);
As usual, the L is loaded while TAD would flip it.  Also, when 0010-0017
are referenced in the deferred state as pointers, the expected PDP-8-like
action is taken; they become auto-increment registers.  This means the
instruction in placed into 0007-0016 so the in-line pointer is in
0010-0017.  One of the KE8E diagnostics actually checks this case!

>   DEFER state (so do MUY and DVI in mode B).

Not really odd at all.  It allows a useful 32K addressing space set of DP
instructions.

I'd like to start some related topics:

Some of the DP instructions demand that the MQA and MQL bits be set.
What actually happens when one or both is left out?  Are any of these
"useful"?

Wasn't there some documentation screwup on one of the DP instructions, I
think DPSZ (double-precision skip if zero)?  (It could have been related
to some aspect of this requirement of MQA and/or MQL.)

>"It's just this little chromium switch over here..."

Please expand on that reference!

cjl

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From: [email-masked] (Charles Lasner)
Date: 4 Mar 1994 06:26:40 GMT

In article <[email-masked]>,
Johnny Billquist <[email-masked]> wrote:
> (Only instruction which might affect

Don't forget DVI!  L set if divide overflow, clear if not.  (Not a DP
instruction!)

cjl

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From: [email-masked] (Bob Supnik)
Date: 3 MAR 94 21:46:51

In article <[email-masked]>, [email-masked] (Johnny Billquist) writes...
>Hmmm, sounds like a nice way to do it anyway.

No, it's done by complementing the subtrahend and setting carry in = 1.
In C terms:

	L'AC = MQ + (AC ^ 07777) + 1

Thus, if MQ = 2, and AC = 1, the calculation is 2 + 7776 + 1 = 1'0001;
if MQ = 2 and AC = 3, the calculation is 2 + 7774 + 1 = 0'7777.  There's
no borrow calculation, only a carry from the add.

This is how most of the early minis, including the NOVA, worked.  The
PDP-11 created a "true" borrow by placing logic between the adder carry
and the condition codes.  For add, PSL.C = adder carry, but for subtract,
PSL.C = ~adder carry.