Subject: simple pdp 'type' computer

From: [email-masked] ("Stephen Walters")
Date: Mon, 30 May 1994 12:45:20 GMT

Does anybody have any article, books, FAQ's, plans for a serial bit 
computer or similar 'simple' machines that can be construted with only 
transistors, ttl 74ls chips or 4000 series CMOS?

This machine would be made of ??? 100+ gates ??? use cassette or acoustic 
delay line for storage.

And....absolutly NO microprocessors
Any suggestions

[email-masked]

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From: [email-masked] (John Wilson)
Date: 30 May 1994 19:47:22 GMT

Someone already told you to look at prints for the '8 etc., and they're
right...  Not to steal the design (that would be pointless and hellish
anyway), but because some of the basic design ideas are cool, they make
it a lot easier to think clearly when you're designing the CPU.
For example, I've seen the 8/L and the 8/E prints and they're surprisingly
similar, the basic idea is to structure your timing a little.  You have
a little state machine with flip flops for each of the "major states"
(on the PDP-8 they're "fetch" (obvious), "defer" (specific to the PDP-8
which is a little strange, it can defer through a memory location yet it
has no immediate mode), "execute" (final cycle of a memory-reference
instruction where it loads or stores the memory operand), and optionally
"break" if a data break cycle is being inserted (which is what DMA was
called when dinosaurs roamed the earth).

So each of these states lasts an entire memory cycle, and there's a
flip-flop for each state which gets a 1 when that state is the current one.
Then there are timing pulses within the memory cycle -- on the PDP-8/E
these are generated by a huge shift register, which has the timing waveform
loaded into it and then clocked through at 20MHz.  The memory cycle is
arbitrarily divided into four timing states, TS1-TS4 (there's a line for
each which gets a 1 during that state).  Then there are the timing pulses,
TP1-TP4, which are each active from one clock before state transitions to
one clock after.  I forget exactly what the timing is, but all these signals
are used to break up the memory cycles in obvious ways, i.e. data read
from core are held valid throughout TS2 (I don't know if that's actually
true) and data to be written are latched on the leading edge of TP4, say.
That kind of thing.

From there on out, everything is done using mostly combinatorial logic
which decodes the instruction register (IR), the major states, and the
timing signals (obviously the major states state machine uses the IR
and the timing signals to decide what state is up next and when to switch
into it).  In the PDP-8 architecture, the 12-bit adder is the star of the
whole show -- almost everything can be aplied to its inputs, including the
constant 0 (and constant 0 or 1 on the carry-in input) -- I think there are
some cases where they just add 0 to a number to get it to appear on the
adder outputs), and then the adder outputs can be latched into almost
any register.  So the adder is used for the TAD (add) instruction, but
also to add 1 to the PC (while fetching and also again for skips), and
to add 1 to the core address (CA) and word count (WC) numbers fetched
from memory during so-called "3-cycle data break", from back when flip-
flops were so expensive that it was worth doing two read-modify-write
cycles before each word read or written via DMA, just to save having
hardware registers for the CA and WC.

One thing that's kind of cute about the PDP-8 is that the "microprogrammable"
(i.e. combinable) "operate" instructions, where for example if you OR the
opcodes for "complement accumulator" and "increment accumulator" it does
both, are defined such that the opcodes are decoded in a certain order so
that the order that they take effect is guaranteed (i.e. complement and
THEN increment will negate a number but not if you do it the other way
around).  On all the real PDP-8s the OPR instructions were in fact executed
in sequential order, but in fact it could all have done using data paths
(i.e., just make sure the adder that does the incrementing (if the IAC
bit is set) is downstream of the XOR gates that do the complementing
(if the CMA bit is set), which in turn is downstream of the AND gates that
do the clearing (if the CLA bit is set), you get the idea (you'd need
muxes to sort out which "group" the instruction is in, but that's very
PDP8-specific).  Now that PALs and FPGAs and so on are cheap you do all
of those instructions using only combinatorial logic, which would greatly
simplify things and reduce the hardare debugging.  Back when the PDP-8s
were designed they were really hell-bent on using that one adder, but as
I said things were amazingly expensive then so it was worth adding a
little sequential logic if it meant you could re-use something.  EAE is
another story of course, doing DVI with combinatorial logic would require
a *big* ROM!

John "my code sucks" Wilson

N.B. all references to actual PDP-8 hardware implementation details are
approximate, it's not like I've ever actually built my own.

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From: [email-masked] (Douglas W. Jones,201H MLH,3193350740,3193382879)
Date: 31 May 1994 02:02:39 GMT

>From article <[email-masked]>,
by [email-masked] ("Stephen Walters"):
> transistors, ttl 74ls chips or 4000 series CMOS ... absolutly NO
> microprocessors

I designed two 16 bit minicomputers that required about 50 SSI and MSI
TTL chips each to implement.  One was an extreme RISC, a move machine,
that is, it had only one instruction, move memory to memory.  It used
memory mapped I/O, and if you wanted to use it to compute anything,
you add a memory mapped ALU and accumulator.  To allow branching, you
need to be able to load the PC with new values, so the PC must also be
memory mapped.  If you build it with multiple accumulators, you can
actually get code densities that approach that of the PDP-11.

The other was a CISC, a microprogrammed stack machine.  It had only
7 instructions (but if you build it, give it 16, it's more fun to
program).  All instructions were 3 (or 4) bits long, and only two were
even vaguely similar (shift 0 into the stack top and shift 1 into the
stack top).  Again, I assumed memory mapped I/O, and I didn't count
I/O device interface complexity in my chip counts.

These processors are documented in:  The Ultimate RISC, Computer
Architecture News, 16, 3 (June 1988) 48-55, and A Minimal CISC,
Computer Architecture News, 16, 3 (June 1988) 56-63.  Computer
Architecture News is the ACM SIGARCH newsletter.

A number of people have built one or another machine based on my
Ultimate RISC design, and the paper may be part of the reason behind
the resurgence of interest in the computer architecture research
community for move machines.  Someone at Cambridge built one that
ran at 1 MIPS, someone else did a gate array (single chip)
implementation running half that speed, and there are others.
MIPS (Silicon Graphics) is apparently toying with the architecture
for some reason (I know because they asked for a copy of my support
package - an assembler and linker).
					Doug Jones
					[email-masked]

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From: [email-masked] (John Wilson)
Date: 31 May 1994 03:03:09 GMT

In article <[email-masked]>,
Douglas W. Jones <[email-masked]> wrote:
[description of kinky minimalist machines deleted]
>(I know because they asked for a copy of my support

The MOV machine sounds like a really cute idea but somehow even
picturing an assembler for one makes me chuckle...  :-)

... parse the mnemonic... look it up on the ST... oh never mind

John Wilson

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From: [email-masked] (Douglas W. Jones,201H MLH,3193350740,3193382879)
Date: 31 May 1994 14:49:27 GMT

>From article <[email-masked]>,
> picturing an assembler for one makes me chuckle...  :-)

I wondered about that too, but I sent MIPS my assembler anyway.  It has
good macro and conditional facilities, and after defining appropriate
macros, you can program the darned move machine as if it was a single
accumulator machine (assuming that's how many accumulators you put in
your memory mapped ALU).
					Doug Jones
					[email-masked]

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From: [email-masked] (Frank R. Borger)
Date: Tue, 31 May 1994 16:14:08 GMT

In article <[email-masked]> [email-masked] (Douglas W. Jones,201H MLH,3193350740,3193382879) writes:

>program).

	Heck, the PDP-8 only had 8 instructions, and one of those was
	HCF, (Halt and Catch Fire!)

Frank R. Borger - Physicist     ___      "I think medical research would show
Michael Reese - U of Chicago   |___       that being a Cubs fan lengthens
Center for Radiation Therapy   | |_) _    your life. Or maybe it just _seems_
net: [email-masked]    | \|_)   longer. " - Mike Royko
ph: 312-791-8075 fa: 791-2517       |_)

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From: [email-masked] (Douglas W. Jones,201H MLH,3193350740,3193382879)
Date: 31 May 1994 18:08:46 GMT

>From article <[email-masked]>,

> 	HCF, (Halt and Catch Fire!)

No, the PDP-8 microprogrammed instructions gave it quite an advantage
over my Minimal CISC.  Also, the PDP-8 has operand fields in each
instruction.  The Minimal CISC has no operand field, only 3 bits of
opcode per instruction, 5 instructions packed per 16 bit word.  Here
are the 8 instructions of the Minimal CISC:

	000 - NOP   No operation (needed because branches are to a
		    16 bit word boundary, and 5 instructions are
		    packed per word).

	001 - DUP   Duplicate the stack top (push a copy of the top
		    word on the stack onto the stack).

	010 - ONE   Shift the stack top left one bit, shifting a one
		    bit into the least significant bit.

	011 - ZERO  Shift the stack top left one bit, shifting a zero
		    bit into the least significant bit.

	100 - LOAD  Replace the top word on the stack with the word
		    in memory to which it points.

	101 - POP   Store the top word on the stack in the location
		    pointed to by the word immediately below it on
		    the stack, and then pop both words off the stack.

	110 - SUB   Subtract the top word on the stack from the word
		    below it, pop both words, and push the difference.

	111 - JPOS  If the word below the stack top is positive, jump
		    to the address pointed to by the top word on the
		    stack.  In all cases, pop both words.

Typical useful instruction sequences are:

	DUP DUP SUB          -- pushes zero on the stack.
	DUP DUP SUB ONE      -- push the constant one on the stack.
	DUP DUP SUB ONE ZERO -- push the constant two on the stack.
	DUP ZERO SUB         -- negate the top word on the stack.
	DUP ZERO SUB SUB     -- add the top two words on the stack.

This instruction set is a real pain to program with until you build up
quite a pile of macros, but then it gets reasonable.  Note that only one
of the above macros takes a full 16 bit word of instruction space!

The microprogram for this instruction set takes 16 words of 21 bit wide
ROM, but if you build it, you're likely to make instructions 4 bits wide
and use up a bit more ROM to make a far more interesting machine.

				Doug Jones
				[email-masked]

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From: [email-masked] ("Stephen Walters")
Date: Tue, 31 May 1994 23:08:34 GMT

Would it make it simpler if the machine was a serial bit processor?