Subject: page wrap for PDP-8?

From: [email-masked] (Michael Bischoff)
Date: 25 Jan 1995 13:44:42 GMT

Hi,
to which page does a 'TAD addr' instruction refer, if
the opcode is at memory address 128*n+127 (decimal)?

Is it the page of the instruction, or the next?

    Michael
--
Michael Bischoff, Abt. Mathematische Optimierung, Pockelsstrasse 14
TU Braunschweig, 38106 Braunschweig, Germany.
e-mail: [email-masked]  Tel: +49-531-391-7555, Fax: +49-531-391-7559

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From: [email-masked] (Douglas W. Jones,201H MLH,3193350740,3193382879)
Date: 27 Jan 1995 17:50:31 GMT

>From article <[email-masked]>,

> the opcode is at memory address 128*n+127 (decimal)?

If you examine the flowcharts of the CPU logic for any PDP-8 model,
you'll find something like this:

    Fetch:
         CPMA = PC
         PC = PC + 1
         MB = MEMORY[CPMA]
         IR = MB<bits 0..2>
         CPMA<bits 5..11> = MB<bits 5..11>
         if MB<bit 4> = 0
           then CPMA<bits 0..5> = 0    -- page zero mode
         if MB<bit 3> = 1
           then begin
             MB = MEMORY[CPMA]
             CPMA = MB
           end

There, PC is the program counter, CPMA is the central processor memory
address register, MB is the memory buffer, and IR is the instruction
register.

As a result of the above, current page mode refers to the page from
which the instruction was fetched.

				Doug Jones
				[email-masked]

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From: [email-masked] (Johnny Billquist)
Date: 28 Jan 1995 12:16:31 +0100

>Is it the page of the instruction, or the next?

It refers to an address on the same page as the instruction.

I think the PC, as all other auto-incrementing stuff is incremented
before it is used.
(Well, okay, the only other auto-incrementing stuff I can remember
off hand is the index registers.)

	Johnny
-- 
Johnny Billquist                  || "I'm on a bus
CS student at Uppsala University  ||  on a psychedelic trip
email: [email-masked]       ||  Reading murder books
pdp is alive!                     ||  tryin' to stay hip" - B. Idol

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From: [email-masked]
Date: 28 Jan 95 19:31:48 MDT

> I think the PC, as all other auto-incrementing stuff is incremented

If that were the case, you would have to enter the address of the 
instruction before the instruction you wanted to start into the switches.

I thought about that sort of thing because on a PDP-5-like processor, if
you extended the autoincrement to include Z 0, you could have immediate
constants. However, it wound up as a special case because of loading
addresses into the PC through the console.

Not that I've done more than think about my PDP-5-in-a-Xilinx mind you
(I've estimated it would take about 300 CLBs).
-- 
----------------+------------------------------------------------------
Roger Ivie      | Don't think of it as a 'new' computer, think of it as
[email-masked] |     'obsolete-ready'