Subject: -8 memory managment question

From: [email-masked] (Olaf Pueschel)
Date: 17 Jan 1995 17:24:07 GMT

Hi folks!
When reading some of the documentation located on Doug Jones *great*
www pages, I ran into the following question:

How are the instruction/data field values handled to form a physical address?

are they a) used to select one of 8 mutually excusive memory banks
         b) prepended to the mem addr to form some sort of segment register
            (yes I worked on 80x86 machines :( )
         c) used in som other magical way?

-olf

PS: are there any other germans out here?
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Olaf P"uschel, Broitzemer Str. 10, 38118 Braunschweig, Germany, +49-531-895643
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  Olaf P"uschel Broitzemer Str. 10 38118 Braunschweig Germany +49 531 895643
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From: [email-masked] (Charles Lasner)
Date: 19 Jan 1995 13:45:44 GMT

In article <[email-masked]>,
>are they a) used to select one of 8 mutually excusive memory banks

On a 32K machine model this is the case.

>         c) used in som other magical way?

There are two different forms of memory beyond 32K.  One is supported by 
two different (incompatible) memory controllers; the second is only 
supported by one of them.

The first is from DEC.  Memory is decoded further into "banks" each 
uniquely containing 32K of 8 fields as in the smaller model.  By careful 
redefinition, an additional addressing bit was inserted into the CIF and 
CDF instructions, and the additional support was added in other 
instructions.  The further additional bit to raise the addressing space 
to 128K is obtained by taking away all IOT's in the range of 630x-637x.  
For compatibility, this second part can be disabled, limiting the 
addressing to 64K.

The second is from CESI.  There are bank registers you have to load with 
additional instructions.  32K remains compatible, as long as you zero out 
the bank extensions.  Again, this gets you to 128K and it is hardware 
compatible with DEC's collections of up-to 128K memory boards.

However, it also supports a different buss decode for up to 512K using 
boards DEC never made.  The programming is essentially the same, only 
"wider" thus occupying more "bank" bits, etc.  (The KT8A buss was defined 
as a 1-of-4 select; the CESI 512K mode makes it a 4-bit encode, etc.)

>Olaf P"uschel, Broitzemer Str. 10, 38118 Braunschweig, Germany, +49-531-895643

cjl

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From: [email-masked] (Johnny Billquist)
Date: 18 Jan 1995 14:40:28 +0100

>         c) used in som other magical way?

Answer is a and b. They are really the same thing.
80x86 machines are a third variety, where the segment is shifted,
and *added* to the virtual address to get the physical address.
(The MMU on the pdp-11 works this way too, as do most modern machines,
the difference being that modern machines have the same size for
virtual and physical addresses).

	Johnny
-- 
Johnny Billquist                  || "I'm on a bus
CS student at Uppsala University  ||  on a psychedelic trip
email: [email-masked]       ||  Reading murder books
pdp is alive!                     ||  tryin' to stay hip" - B. Idol

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From: [email-masked] (Bill Haygood)
Date: 20 Jan 1995 00:27:00 GMT

Olaf Pueschel ([email-masked]) wrote:

: How are the instruction/data field values handled to form a physical address?
: are they a) used to select one of 8 mutually excusive memory banks

On *indirect* AND, TAD, ISZ and DCA instructions only, the PDP-8 locates 
the field relative address (low order 12 bits) of the operand by fetching 
it either from the current instruction field page or page zero of the 
current instruction field.  The machine then prepends the DF to this 
12-bit address and the operand gets fetched from that address.  For all 
other *indirect* (and *all* direct instructions), the DF does not come 
into play.

:          b) prepended to the mem addr to form some sort of segment register
:             (yes I worked on 80x86 machines :( )

In the PDP-8, since the DF always gets "prepended" rather than shifted a 
few bits (as in the 80x86 uprocs), I personally find the PDP-8 scheme 
much easier to understand.  For example, in the PDP-8, one specifies an 
absolute address as a 5-digit octal number: 41600 (field 4, relative 
address 1600).  We generally don't use any other way to specify an 
absolute address.  In the Intel 80x86 uprocs, OTOH, you could specify 
absolute address 45678 as segment 4000, offset 5678 or as segment 4001,
offset 5668, or as segment 4002, offset 5658, or as segment 4100, 
offset 4678, ... (this could really get tedious after a while!).  (I once 
has to write a subroutine to return a true or false as to whether two 
80x86 addresses matched or not [given segment,offset as input]!)

:          c) used in som other magical way?

To many of us, the PDP-8 == pure magic!  After all, some consider 
the -8 as the very first RISC machine!

If either Bob Supnik at DEC and/or cjl at sunsite and/or anyone else 
read(s) this post, please feel free to critique my understanding of 
the DF register as outlined above.

Bill