Subject: Re: Emulators

From: [email-masked] (Douglas W. Jones,201H MLH,3193350740,3193382879)
Date: 22 Feb 1995 14:55:13 GMT

>From article <[email-masked]>, by [email-masked] (Stephen Pratt):
> If I issue the following sequence on a PDP8/e - does the interrupt
> system end up enabled or disabled?
> 
> ION
> IOF

The answer is in Figure 3-99 in the PDP-8/E Maintenance Manual, Volume I,
April 1971 edition.

  ION enables interrupts with a one instruction delay by
       setting the interrupt enable flipflop, which is clocked
       into the interrupt delay flipflop one instruction later;
       the output of the interrupt delay flipflop actually controls
       whether interrupts are enabled.
  IOF disables interrupts by resetting both the interrupt enable
       and interrupt disable flipflops.

Therefore, the sequence ION;IOF leaves interrupts disabled.

				Doug Jones
				[email-masked]

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From: [email-masked] (Stephen Pratt)
Date: 21 Feb 1995 20:01:50 GMT

If I issue the following sequence on a PDP8/e - does the interrupt system end up
enabled or disabled?

ION
IOF

Cheers

Stephen
-- 
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Stephen Pratt  34 Grantchester Street CAMBRIDGE CB3 9HY

'The discerning heart seeks knowledge'
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From: [email-masked] (Charles Lasner)
Date: 24 Feb 1995 16:02:44 GMT

In article <[email-masked]>,
>       and interrupt disable flipflops.
                      ^^^^^^^ delay

IOF turns off interrupts immediately regardless of whether they were 
pending or not.  ION turns interrupts on after a one-instruction delay.

However, if there is an extended memory control present, then CIF, or any 
other instruction that loads the instruction field, will inhibit 
interrupts from occurring until the next JMP or JMS occurs.

On the PDP-8/e and -8/a, RTF enables interrupts and also causes the same 
one instruction delay.  This is to ensure that a 4K -8/e or -8/a without 
an extended memory controller still gets the one-instruction interrupt 
delay.  Thus, if extended memory control is also present, interrupt gets 
enabled, one-instruction delayed, and also inhibited, all at the same time.

The usual sequence of instructions is

	RTF
	CLA
	JMP I	xxxx

The CLA is necessary because the AC contained the reload value, 
presumably from a former GTF at the point of interrupt.  Practical 
interrupt handlers also need something like TAD SAVEAC after the CLA to 
reload the AC to what it was before the interrupt as well, etc.  The xxxx 
is usually 0000 in a simple interrupt handler, but stack-oriented 
interrupt handlers (where an interrupt routine is itself interruptible 
after it clears the source of the interrupt but not yet has handled the 
consequences, etc.) may pull the return address off of a stack, and thus 
need not use 0000.

On the 6120, it works a bit different.  The GTF instruction always reads 
back a 1 in the bit which on the -8'e is the "is interrupt on" (bit[4]).  
Thus, when RTF is executed, this bit is a 1.  The 6120 RTF doesn't 
necessarily enable interrupts unless this AC bit is set, else it clears 
it.  But since the GTF sets the bit to a one, the combination works 
effectively the same as on the -8's.

Additionally, the 6120 RTF clears the AC, thus 6120-specific interrupt 
routines can be one instruction shorter eliminating the CLA after the RTF.

On the front panels of the Omnibus machines, you can see the "no int" 
bit[3].  But the instructions such as GTF *do not* read the bit back.  
The manual is wrong on this point since it claims that it does happen, 
but said claim is false.  The -8/e diagnostics won't work if you follow 
the manual!  The *light* will come on if you execute CIF or RMF or RTF, 
etc. but you cannot read it back with an instruction.  On the 6120, GTF 
and GCF read this bit as a 0 always as well etc.

The designers of the PCM-12 6100 machines got "bit" on this point as 
well.  They designed a board that went by the manual.  As a result, it 
can't pass some diagnostics.  The added a jumper to to it the "right" way 
or the "DEC" way.

On the Intercept or PCM-12 6100 machines, the front panel is emulated in
software using a variable clock that causes CP interrupts.  The faster it
updates, the slower the effective -8 speed is, and you can also disable it
if desired, etc..  Unless you enable the bit to read back the no int state
with GTF (which is part of the CP front panel routines), the front panel 
won't light the no int light when it ought to!

I have written some code for a PDP-12 with a minimum of 4K.  Some of it 
is interrupt driven, and in spots uses LINC instructions.  The LINC is 
not only incompatible, it has its own interrupt location (00040) and 
rarely is LINC interrupt uses.  Thus, LINC code has to prevent interrupts 
in general.

The ION one instruction delay is insufficient since LINC code tends to be 
several instructions long before returning to PDP-8 mode.  IOF in front 
of the code is unacceptable because you cannot know the former state of 
the interrupt within this code.  (On the -8/e, you can use SKON to 
determine whether to restore interrupts later.)

Well, it turns out that even a 4K PDP-12 has extended memory control!  
Just use CIF 00 in front of the LINC instruction etc. and it can't be 
interrupted.  (Note: LINC JMP instructions must be avoided!)  (Note: the 
LINC instruction set is 1K oriented with a 1K data field.  Thus even a 4K 
-12 is considered to have extended memory.  If a PDP-8 interrupt routine 
fails to perform the appropriate RMF instruction, it won't restore the 
LINC extensions to the appropriate 1K-oriented values.  The PDP-8 
extended memory instructions have been modified to incorporate the LINC 
1K extensions for interrupt purposes.  Thus, RMF restores more than just 
the PDP-8 IF and DF, etc.  So, as a result, CIF was implemented with 
interrupt inhibit even in the basic machine, etc.  Should a LINC JMP 
instruction occur after a CIF, you wind up in the 0th quarter of LINC 
memory, an unwanted quirk!  Thus, short LINC sequences better not use JMP 
if after CIF.  Interrupt routines must use RMF to completely restore the 
LINC memory considerations.  Alternatively, a complicated routine could 
be written using the extended definition of RIB for the PDP-12 which 
reads back the LINC memory quarter values as well as the PDP-8 values for 
32K by fields.  Appropriate instructions could then be created in-line to 
deal with it.  But it's a whole lot easier to just use RMF, and 
additionally is compatible with the same code for straight PDP-8 
operation.  All of this is prior to the Omnibus style of the GTF/RTF 
sequence, and is the only way to write generic interrupt routines for all 
PDP-8 models, such as is found in FOCAL, 1969 etc.)

cjl