Subject: Re: Emulators

From: [email-masked] (Douglas W. Jones,201H MLH,3193350740,3193382879)
Date: 14 Feb 1995 15:43:35 GMT

>From article <[email-masked]>,
by [email-masked] (Stephen Pratt):

> what exactly is the operation of the CAF instruction.

CAF is exactly the same as hitting the CLEAR switch on the front panel.
I checked the schematic to verify this!  AC and LINK are cleared;
PC is not changed.  The INITIALIZE signal goes to each device.  The
documentation is indeed vague about whether or not this disables
interrupts, but the schematics make it clear that the INITIALIZE signal
does disable interrupts!  My emulator does the following:

        link = 000000;
        ac = 00000;
        irq = 0;
        enab = 0;
        enab_del = 0;

Note that the initialize signal also has an effect on each device, and
that the response of the device is arbitrary and defined by the device
designer -- you've got to read the writeup on each device you emulate
to see if this causes that device to enable or disable interrupts.

The standard is that the device ready and done flags are reset and the
device specific interrupt enable flag is set, but not all devices conform
to this standard!
> 
> Also could someone fill me in on the exact meanings of bits 3 and 4
> of the flags register as listed on page 3.14 of the 'Small Computer
> Handbook'?

I'd love to help, but what edition of the Small Computer Handbook are
you referring to?  I've got just about all of them at home, but the copy
I have at work (1973) has no flags register on page 3-14.  If you mean
the flags register returned by GTF, page 4-8 of the 1973 handbook gives
these as:

          AC3 = interrupt inhibit flipflop
          AC4 = interrupt enable flipflop

The interrupt enable flipflop is the one set and reset by the ION and IOF
instructions.  Usually, it's the only one you care about.  The interrupt
inhibit flipflop belongs to the KM8E memory management unit.  My schematics
for that are at home, so I can't answer definitively, but note that many
KM8E instructions inhibit interrupts until the next JMP or JMS instruction.
I believe that is the function of the inhibit flipflop.

If you haven't looked at the documentation available from my web page,
check out

   http://www.cs.uiowa.edu/~jones/pdp8/index.html

Among other things, you'll find a fairly well developed PDP-8 emulator
there, with complete and fairly good support for X-windows.

				Doug Jones
				[email-masked]

---

From: [email-masked] (Charles Lasner)
Date: 16 Feb 1995 05:09:33 GMT

In article <[email-masked]>,
>          AC4 = interrupt enable flipflop

Actually, there is a problem here.  There are actually three variations:

1)	The paper version of the PDP-8/e manual.

2)	The real hardware of the PDP-8/e computer.

3)	The revised nature of how the 6120 handles this differently.

The PDP-8/e manual claims that the interrupt inhibit flip-flip can be 
read back with GTF.  You can see the bit on the front panel, but you 
cannot read it back in the hardware.  Several diagnostics pragmatically 
check for it to be that way.

The designers of the PCM-12 6100-based machine rolled their own extended 
memory hardware.  They assumed the manual was correct, but then their 
machine flunked the diagnostics.  So they added a jumper to make it the 
"right" way or the "DEC" way.   So on that machine, you can do it as 
documented or compatibly deficient, your choice.

On the 6120, things are a bit different.  To avoid the entire mess, 
bit[3] is the power-on flip-flip, which just means that you haven't 
issued a CAF yet, and are in the state of POST, so you can allow yourself 
some once-only initialization, etc.

Bit[4] on the 6120 reads back a 1 always.  The reason is the differing 
behavior for RTF.  On the -8/e, RTF always enables interrupt.  On the 
6120, RTF loads AC[4] into the ION flip-flop.  This way, interrupt 
sequences that start with GTF and end with RTF are compatible, although 
what's happening in bit[4] is quite different fore and aft!

A related change: the 6120 clears the AC after the RTF.  A good thing, 
since by definition this information is worthless (it is always loaded 
from a saved copy in memory my nature, thus this makes the interrupt 
handler a cycle/instruction shorter.).  But for compatibility with the 
-8/e, you have to do a CLA after the RTF anyway, thus this is only for 
truly 6120-based interrupt routines, etc.  In any case, all machines 
agree that RTF inhibits interrupts until the next JMP or JMS (assuming 
RTF did enable the interrupt, an issue only on the 6120.)

BTW, the 6120 also has GCF, get current fields.  Same layout as GTF, but 
it's the current info, not what's saved on an interrupt.

I guess they had to do something with all of those extra instructions 
returned by no possibility of KT8A or time-share trap compatibility :-).

cjl

---

From: [email-masked] (Stephen Pratt)
Date: 14 Feb 1995 11:47:41 GMT

I am currently writing an emulator for the PDP8/e

Please could someone out there help me with the following:

what exactly is the operation of the CAF instruction. Specifically, does it have
any effect on the interrupt system, in the way of enabling/disabling interrupts?

Also could someone fill me in on the exact meanings of bits 3 and 4 of the flags
register as listed on page 3.14 of the 'Small Computer Handbook'?

Thank you

-- 
-----------------------------------------------------------------------
Stephen Pratt  34 Grantchester Street CAMBRIDGE CB3 9HY

'The discerning heart seeks knowledge'
-----------------------------------------------------------------------