From Steven.D.Ligett@Dartmouth.EDU Fri Jun 25 15:19:14 1993
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Date: 25 Jun 93 09:17:15 EDT
From: Steven.D.Ligett@Dartmouth.EDU (Steven D. Ligett)
Subject: The MIPs design I've been working on
To: riscy@pyramid.com (Mips 3000)
Status: RO
X-Status: 

I've been noodling along on a design for a MIPS box based on the IDT chips
for the past two years.  Some folks ideas here have been along the same
lines, what with serial I/O processors, etc., so I'll outline where my design
is.  Any details are subject to change, of course.  Let me first draw a
simple picture.

   +-----+     +-----+     +-----+
   | 3081|     | RAM |     |     |     
   | or  |<--->| and |<--->| 3041|     
   | 3051|     | VRAM|     |     |
   +-----+     +-----+     +-----+
                  |           |
               +-----+     +-----+
               |RAM- |     | I/O |     
               | DAC |     | and |     
               |     |     |EPROM|
               +-----+     +-----+

The main cpu is a 3051 @ 20 mhz or a 3081 @ 40 mhz.  The main cpu is
connected ONLY to the RAM and VRAM.  Three 72-pin SIMMs for the RAM (up to 96
MB, if you can afford 32 MB SIMMs).  VRAM composed of Mac compatible SIMMs;
either 512 KB or 1 MB.

All the I/O goes through the 3041 @ 20 mhz.  Basically, the 3041 is a smart
DMA controller for the 3081.  There's a 53c94 SCSI chip on a 16-bit bus, some
26c94 quad uarts on an 8-bit bus, one boot eprom on the 8-bit bus, and some
slots.  The slots are a simple 8-bit bus, 36 pins, giving up to about
10MB/sec off the 3041.  The 3041 invisibly (to the software) handles 8, 16,
and 32 bits tranfers.

The RAMDAC is in the TI 34076 family, which cost from $15 on up, depending on
speed, features, etc.  Timing is handled by a NSC chip whose number escapes
me at the moment.

 
From drew@caesar.cs.Colorado.EDU Fri Jun 25 16:49:42 1993
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To: riscy@pyramid.com, Steven.D.Ligett@dartmouth.edu (Steven D. Ligett)
Subject: Re: The MIPs design I've been working on 
In-Reply-To: Your message of "25 Jun 1993 09:17:15 EDT."
             <5264379@prancer.Dartmouth.EDU> 
Date: Fri, 25 Jun 1993 08:48:32 -0600
From: Drew Eckhardt <drew@caesar.cs.Colorado.EDU>
Status: RO
X-Status: 



    I've been noodling along on a design for a MIPS box based on the IDT chips
    for the past two years.  Some folks ideas here have been along the same
    lines, what with serial I/O processors, etc., so I'll outline where my desi
   gn
    is.  Any details are subject to change, of course.  Let me first draw a
    simple picture.
    
       +-----+     +-----+     +-----+
       | 3081|     | RAM |     |     |     
       | or  |<--->| and |<--->| 3041|     
       | 3051|     | VRAM|     |     |
       +-----+     +-----+     +-----+
                      |           |
                   +-----+     +-----+
                   |RAM- |     | I/O |     
                   | DAC |     | and |     
                   |     |     |EPROM|
                   +-----+     +-----+
    
    The main cpu is a 3051 @ 20 mhz or a 3081 @ 40 mhz.  The main cpu is
    connected ONLY to the RAM and VRAM.  Three 72-pin SIMMs for the RAM (up to 
   96
    MB, if you can afford 32 MB SIMMs).  

Since normal humans can't afford the 25ns memory to run 0ws, 
we need to run with wait states (which kill performance) =8^)
Interleaving can cut the number of waitstates, but we can't do it 
if our memory is all on a single 32 bit SIMM. 

    VRAM composed of Mac compatible SIMMs;
    either 512 KB or 1 MB.

Are you talking VRAM, or DRAM?  The former is inherently dual 
ported, and keeps the video hardware from eating over half our memory
bandwidth.  If we're using the later, how have you isolated it from the 
main bus? 
    
    All the I/O goes through the 3041 @ 20 mhz.  Basically, the 3041 is a smart
    DMA controller for the 3081.  There's a 53c94 SCSI chip on a 16-bit bus, so
   me
    26c94 quad uarts on an 8-bit bus

I'm not familiar with this chip.  How big are the buffers (very important
if it's entirely interrupt driven),  and will it interface with a DMA 
controller?

  one boot eprom on the 8-bit bus, and some
    slots.  The slots are a simple 8-bit bus, 36 pins, giving up to about
    10MB/sec off the 3041.  

A propriety 8-bit bus is a neat idea - we get some breathing room for 
second ethernet boards, etc, but don't have to jump through hoops doing
ISA compatability.

Along these lines, another thing that may be worth considering to satisfy
the anti-ethernet/uart/etc minimalists would be including sockets, address
decoding, and glue for these parts but leaving the sockets empty on one 
set of boards.
    
    The RAMDAC is in the TI 34076 family, which cost from $15 on up, depending 
   on
    speed, features, etc.  Timing is handled by a NSC chip whose number escapes
    me at the moment.

Is the TI 34076 whatever a CRT controller and a RAM DAC (ie pallette chip)?
If it's the later, what are you driving it with?

--------


 
From Steven.D.Ligett@Dartmouth.EDU Fri Jun 25 17:21:18 1993
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Date: 25 Jun 93 11:19:32 EDT
From: Steven.D.Ligett@Dartmouth.EDU (Steven D. Ligett)
Subject: Re: The MIPs design I've been working on 
To: riscy@pyramid.com
Status: RO
X-Status: 

Drew Eckhardt asked some questions about the simple explanation of the design
I threw out:

(on memory system design)
1) Since normal humans can't afford the 25ns memory to run 0ws, 
we need to run with wait states (which kill performance) =8^)
Interleaving can cut the number of waitstates, but we can't do it 
if our memory is all on a single 32 bit SIMM. 

My goal is cheap.  The memory is not interleaved.  Both cpus share the ram,
but the 3041 is expected to run its little DMA code out of cache most of the
time.  Also, the Vram is on the same bus.  cheap.

(really Vram?)
2) Are you talking VRAM, or DRAM?  The former is inherently dual 
ported, and keeps the video hardware from eating over half our memory
bandwidth.  If we're using the later, how have you isolated it from the 
main bus? 

Vram SIMMs.  All current Macs use them - giving us low cost, and availability
due to volume, and availability.  cheap.

(on the Philips (signetics) Uart)
3) I'm not familiar with this chip.  How big are the buffers (very important
if it's entirely interrupt driven),  and will it interface with a DMA 
controller?

Quad uart.  52 pin plcc.  8 byte fifos for each channel's receive and xmit
channels.  I mean, 8 for each receive, and 8 for each xmit.  Programmable
fifo interrupt thresholds.  (One instruction on the 3041 will read/write 4
bytes.)  Four pins per channel for modem controls.  Biggest lack - arbitrary
baud rates.  There are six sets of baud rates, and pairs of channels share
sets of rates.  Within a pair, any xmitter or xrcvr can have any rate from
the set.  $24.  cheap.

(on the I/O bus)
4) A propriety 8-bit bus is a neat idea - we get some breathing room for 
second ethernet boards, etc, but don't have to jump through hoops doing
ISA compatability.

Along these lines, another thing that may be worth considering to satisfy
the anti-ethernet/uart/etc minimalists would be including sockets, address
decoding, and glue for these parts but leaving the sockets empty on one 
set of boards.

Aside from the scsi, and one or two quad uarts, I don't see putting much I/O
on the board.  An RTC/eeprom.  I'd have to be convinced that ethernet needs
to be on the motherboard.  The I/O bus is JUST for I/O I don't have my notes
with me, but it's 8 data lines, a small number of address lines, +12, +5,
-12, grounds, clock, and some handshake lines.  Each slot is decoded into a
separate address block.  That is, the handshake lines aren't bussed - they're
decoded.

(on the video)
5) Is the TI 34076 whatever a CRT controller and a RAM DAC (ie pallette
chip)?
If it's the later, what are you driving it with?

It's a ramdac - the NSC timing chip controls - well, it controls the timing! 
:-)  An 80 mhz clock would drive the pixels (1024x768), and provide the
processor clocks as well.  Would have space for other oscillators on the
board.  I'll dig up the NSC chip info.  The 34076 does the ordinary 1, 2, 4,
or 8 to 24 bit table lookups.


 
