|
|
| Address
(octal) |
Name |
Description |
| 00 |
A |
The "accumulator". Almost
every AGC instruction uses or modifies the accumulator in some
way. The accumulator differs from all other memory or i/o
locations addressed by the CPU, in that it is a 16-bit register rather than a
15-bit register. In most cases this is transparent to the
programmer, because the 16th bit is not directly observable or
modifiable, and because data within the accumulator is automatically
adjusted to 15 bits before most uses of it. The 16th bit is
present in order to allow detection of arithmetical overflow or
underflow. Internally, when there is no overflow, the 16th bit of the accumulator is a duplicate of the 15th (sign) bit. When a value is loaded into the accumulator from memory, the value is sign-extended from the 15th bit to the 16th bit. In other words, for positive values the 15th and 16th bits are both 0, while for negative values they are both 1. When overflow occurs, however, the 15th and 16th bits differ: After an operation that causes positive overflow, the 16th bit is 0 and the 15th bit is 1. After an operation that causes negative overflow, the 16th bit is 1 and the 15th bit is 0. Various CPU instructions can detect overflow and alter their actions somewhat upon finding it. The TS (transfer to storage) instruction is notable in this regard, because it can actually be used to provide a branch upon detection of overflow. In most cases, when data is transferred out of the accumulator to a true 15-bit register, it is overflow-corrected. Overflow-correction implies:
|
| 01 |
L |
Like the accumulator, this is a 16-bit register rather than a
15-bit register. This means, for example, that like the
accumulator you can generate overflow conditions with instructions like
ADS L; also, the
overflow can be transferred between the accumulator and L with
instructions like XCH L
or LXCH A. This is the "lower product register". This is a general-purpose register, but many instructions pair it with the accumulator in cases where double precision (DP) operations are performed. In these cases, the A register holds the more-significant word, and the L register holds the less-significant word. Note that erasable-memory location 01 is automatically duplicated as i/o channel 01, and vice-versa. |
| 02 |
Q |
Like the accumulator, this is a 16-bit register rather than a
15-bit register. This means, for example, that like the
accumulator you can generate overflow conditions with instructions like
ADS Q; also, the
overflow can be transferred between the accumulator and Q with
instructions like XCH Q
or QXCH A. This register is intended to store return addresses of called procedures. Note that the AGC CPU has no hardware stack, and provides only a single memory location (the Q register) for storing return addresses. Therefore, it is not possible to have nested procedure calls unless the contents of the Q register are stored prior to calling a procedure and then restored after the procedure returns. The CPU's instruction TC is used to call a procedure, and the instruction automatically updates the Q register; similarly, the RETURN instruction returns from a called procedure by placing the contents of the Q register into the program-counter register. Note that erasable-memory location 02 is automatically duplicated as i/o channel 02, and vice-versa. |
| 03 |
EB |
The "erasable bank
register". This register contains a 3-bit field that determines
which of the 8 banks of erasable memory (see "Memory Map" below) is
mapped into the address range 1400-1777 (octal). The 15 bits of
the EB register are arranged as follows: 000 0EE E00 000 000
where EEE are the bank-selector bits.Note that the EEE field of the EB register is duplicated into the BB register (see below). Changes to the EB register are immediately automatically mirrored in the BB register, and vice-versa. |
| 04 |
FB |
The "fixed bank register".
This register contains a 5-bit field that determines which of the 36
banks of fixed memory (see "Memory Map" below) is mapped into the
address range 2000-3777 (octal). 5 bits are not, of course,
adequate for selecting among 36 banks, so these 5 bits are supplemented
by a 6th bit (the "super bank" bit) from i/o channel 7. In most
cases, the superbank bit is 0, and so the 5-bit field in the FB
register simply selects from among banks 0-37 (octal). When the
superbank bit is 1, on the other hand, the 5 bits of the FB register
actually select from among banks 0, 1, ..., 27, 40, 41, ..., 47; i.e.,
bank-selection is the same as when the superbank bit is 0, except that
banks 40-47 are used instead of 30-37. Banks 44-47
don't actually exist within the AGC, and so it is mere supposition on
my part that they would be selected. The 15 bits of the FB register are arranged as follows: FFF FF0 000 000 000
where FFFFF are the bank-selector bits.Note that the FFFFF field of the FB register is duplicated into the BB register (see below). Changes to the FB register are immediately automatically mirrored in the BB register, and vice-versa. Refer also to i/o channel 07. |
| 05 |
Z |
The program-counter
register. This 12-bit register always indicates the next
instruction to be executed. It is always updated prior to executing the instruction,
so that an instruction which saved the value of the Z register would
actually be the address of the next instruction in memory. Obviously, a 12-bit register cannot address all of memory. Full addresses are formed by combining the 12-bits of the Z register with the 3 bits of the EB register, the 5 bits of the FB register, and the superbank bit of i/o channel 7. (Refer to "Memory Map" below, and to the descriptions of the EB and FB registers above.) 12 bits can represent values from 0-7777 (octal), and these are interpreted as follows:
|
| 06 |
BB |
The "both banks register".
This register contains a 3-bit field duplicating the EEE field of the
EB register, and a 5-bit field duplicating the FFFFF field of the FB
register. Changes in the EB and FB registers are immediately
automatically mirrored in the BB register, and vice-versa. The
bits are arranged within the register as follows: FFF FF0 000 000 EEE
Refer also to i/o
channel 07. |
| 07 |
(no name) |
This location is not associated
with core memory, but is hardwired to 0. In other words, it
always contains
the value 00000. It is very useful as a source of zeroes, because
most AGC instructions have no "immediate" addressing mode.
(In other words, you can't use a specific numerical value as an
operand, but can only use the address of a memory location as an
operand.) |
| 10 |
ARUPT |
This register is provided as a
convenient location for storing the value of the A register during an
interrupt service routine. However, vectoring to the interrupt
does not automatically load this register, nor does returning from the
interrupt-service routine restore the A register from ARUPT.
These actions must be done under program control by the interrupt
service routine. Interrupts are automatically disabled while
overflow is present in the accumulator, so transfer of data back and
forth between A (16 bits) and ARUPT (15 bits) does not result in loss
of overflow indications. |
| 11 |
LRUPT |
This register is provided as a convenient location for storing the value of the L register during an interrupt service routine. However, vectoring to the interrupt does not automatically load this register, nor does returning from the interrupt-service routine restore the L register from LRUPT. These actions must be done under program control by the interrupt service routine. |
| 12 |
QRUPT |
This register is provided as a convenient location for storing the value of the Q register during an interrupt service routine. However, vectoring to the interrupt does not automatically load this register, nor does returning from the interrupt-service routine restore the Q register from QRUPT. These actions must be done under program control by the interrupt service routine. |
| 13-14 |
(spares) |
|
| 15 |
ZRUPT |
This register stores the return
address of an interrupt service routine. When the CPU vectors to
an interrupt service routine, it automatically transfers the value of
the Z register (the program counter) into the ZRUPT register.
When the interrupt-service routine returns, using the RESUME
instruction, the value of ZRUPT is automatically transferred back into
the Z register. |
| 16 |
BBRUPT |
This register is provided as a convenient location for storing the value of the BB register during an interrupt service routine. However, vectoring to the interrupt does not automatically load this register, nor does returning from the interrupt-service routine restore the BB register from BBRUPT. These actions must be done under program control by the interrupt service routine. |
| 17 |
BRUPT |
(Note:
As of 20050820, I no longer perform the instruction substitution
described below. The internal mechanics of yaAGC are sufficiently
different from the true AGC CPU that it should not been needed. I
may restore it later.) This register stores the value stored at the return address of an interrupt service routine. In other words, it is the instruction (not the address of the instruction) which will be executed when the interrupt-service routine returns. When the CPU vectors to an interrupt service routine, it automatically loads this register. When the interrupt-service routine returns, using the RESUME instruction, the value found in the BRUPT register will be used as the next instruction. It may seem from this description that an interrupt service routine can return to a position in memory from which the interrupt vector occurred, but can arrange to execute an entirely different instruction than what is found at that address. I believe that this statement is true, and obviously such a feature would need to be used with great care. (However, I don't believe that the BRUPT register was really provided for this purpose; I believe that the BRUPT register exists for the purpose of holding instruction which have been altered by a preceding INDEX instruction, as described below under the discussion of the instruction set. The true AGC allowed interrupts to occur between an INDEX instruction and the instruction affected by the INDEX instruction, and so this provision was necessary. However, yaAGC does not allow such interrupts, and conflicts between INDEX and the interrupt system do not arise in yaAGC.) |
| 20 |
CYR |
The "cycle right register",
which is one of the four so-called "editing" registers. When a
value
is written to this register, the value is automatically cycled
right (with the least significant bit, bit 1, wrapping into bit
15).
For example, if the software attempted to write the following bits to
the CYR register, abc def ghi jkl mno
then the value actually stored in the CYR register would beoab cde fgh ijk lmn
|
| 21 |
SR |
The "shift right register",
which is one of the four so-called "editing"
registers. When a value is written to this register, the
value is
automatically shifted right (with the most significant bit, bit 15,
being duplicated into bit 14,and the least significant bit, bit 1,
being discarded). For example, if the software attempted to
write the following bits into the SR
register, abc def ghi jkl mno
then the value actually stored in the SR register would be:aab cde fgh ijk lmn
This operation corresponds arithmetically to division of a
single-precision (SP) value by 2, as it automatically sign-extends the
result. |
| 22 |
CYL |
The "cycle left register", which
is one of the four so-called "editing"
registers. When a value is read back from this register, the
value is
automatically cycled left (with the most significant bit, bit 15,
wrapping into bit 1). For example, if before readback the
CYL
register
contained the bits abc def ghi jkl mno
then the value actually stored in the CYL register would be:bcd efg hij klm noa
|
| 23 |
EDOP |
The "edit polish opcode
register", which is one of the four so-called "editing"
registers. This register is used mainly by the interpreter for
decoding interpreted instructions (which are packed two to a word), and
has little value for other purposes. When a value is written to
this register, it is automatically shifted right 7 positions, and the
upper 8 bits are zeroed. Actually, the contents of the bits 8-15
in the
edited result are undefined, as far as I can tell, and making them zero
is my own requirement. For example, if the software attempts to write the following bits into the EDOP register, abc def ghi jkl mno
then the value actually stored in the EDOP register would be:000 000
00b cde fgh
|
| 24 |
TIME2 |
TIME1 is
a 15-bit 1's-complement counter which is incremented every 10
ms. TIME1 by itself overflows every 214*10 ms., or 163.84
seconds. Upon overflow of TIME1, the 14-bit counter TIME2 is
automatically incremented. Thus, the two counters together form a
28-bit value which can keep track of time for up to 228*10
ms., or just over 31 days. The TIME1/TIME2 register pair acts as
a master clock for the AGC. yaAGC internally clocks this counter. |
| 25 |
TIME1 |
|
| 26 |
TIME3 |
TIME3 is a 15-bit 1's-complement
counter which is incremented every 10 ms. Upon
overflow, it requests an interrupt (T3RUPT), which results in vectoring
to the interrupt service routine at address 4014 (octal). This
interrupt is used by the "wait-list" for scheduling
multi-tasking. Incrementing TIME3 is 5 ms. out of phase with incrementing TIME4, so if their respecitve interrupt service routines don't take longer than 4 ms. to execute, the interrupts for the two will not conflict. Software typically uses this counter by having the interrupt service routine reload the counter with a value chosen to insure that the interrupts occur at a desired rate. For example, to make an interrupt occur once per second, at every interrupt the counter would be reloaded with 214-100=16284 (decimal). Because 10 ms. is usually much longer than the amount of time needed to vector to the interrupt service routine, it is unnecessary in such calculations to account for the time taken by the interrupt vectoring. yaAGC internally clocks this counter. |
| 27 |
TIME4 |
TIME4 is a 15-bit 1's-complement
counter which is incremented
every 10 ms. Upon overflow, it requests an interrupt (T4RUPT),
which results in vectoring to the interrupt service routine at address
4020 (octal). The T4RUPT program services the DSKY's
display. (It does not service DSKY keypad.) Incrementing TIME3 is 5 ms. out of phase with incrementing TIME4, so if their respecitve interrupt service routines don't take longer than 4 ms. to execute, the interrupts for the two will not conflict. Software typically uses this counter by having the interrupt service routine reload the counter with a value chosen to insure that the interrupts occur at a desired rate. For example, to make an interrupt occur once per second, at every interrupt the counter would be reloaded with 214-100=16284 (decimal). Because 10 ms. is usually much longer than the amount of time needed to vector to the interrupt service routine, it is unnecessary in such calculations to account for the time taken by the interrupt vectoring. yaAGC internally clocks this counter. |
| 30 |
TIME5 |
TIME5 is a 15-bit 1's-complement
counter which is incremented
every 10 ms. Upon overflow, it requests an interrupt (T5RUPT),
which results in vectoring to the interrupt service routine at address
4010 (octal). This is used by the digital autopilot (DAP) Software typically uses this counter by having the interrupt service routine reload the counter with a value chosen to insure that the interrupts occur at a desired rate. For example, to make an interrupt occur once per second, at every interrupt the counter would be reloaded with 214-100=16284 (decimal). Because 10 ms. is usually much longer than the amount of time needed to vector to the interrupt service routine, it is unnecessary in such calculations to account for the time taken by the interrupt vectoring. yaAGC internally clocks this counter. |
| 31 |
TIME6 |
TIME6 is a 15-bit 1's-complement
counter which is updated
every 1/1600 second by means of a DINC
unprogrammed sequence.
There is a
CPU flag which can mask counting of TIME6 on or off. By
writing 1 to
bit 15 of i/o channel 13 (octal), TIME6 counting is enabled;
conversely, by
writing 0 to that bit, the TIME6 counting is disabled. Upon
reaching ±0, the counter requests an interrupt
(T6RUPT),
which results in vectoring to the interrupt service routine at address
4004 (octal), and then turns off the T6RUPT counter-enable bit. The T6RUPT is used by the digital autopilot (DAP) of the LM to control the jets of the reaction control system (RCS). Thus a typical use might be:
|
| 32 |
CDUX |
These
counters are used to monitor the orientation of the spacecraft.
Three Control Data Units (CDUs) are dedicated to measuring the 3 gimbal
angles in the Inertial Measurement Unit (IMU). CDUX refers to the
"inner" gimbal angle, CDUY refers to the "middle" gimbal angle, and
CDUZ refers to the "outer" gimbal angle. The CDUs are like analog-to-digital converters, and convert the analog angles to digital data comprehended by the CPU. The IMU provides a measurement platform which is stable with respect to the fixed stars, and maintains its orientation with respect to the stars even while the spacecraft itself rotates. The platform is physically mounted on gimbals, and by measuring the gimbal angles, the orientation of the spacecraft with respect to the IMU's stable platform can be deduced by calculation. (Because only 3 gimbals were used, it was possible for the spacecraft to rotate into positions beyond which the stable platform could no longer maintain its stability with respect to the fixed stars, and would thus begin to rotate with the spacecraft. This condition, "gimbal lock", resulted in an inability to continue monitoring spacecraft orientation and acceleration, and required re-entry of all orientation, position, and velocity data into the computer system. A 4th gimbal would have prevented gimbal lock, but was not provided for some reason.) These counters contain 15-bit 2's-complement unsigned values, and therefore can take values ranging from 0 to 32767 (decimal). The counters are processed with the PCDU unprogrammed sequence (see below) in order to increase the angles by one unit, and are processed with the MCDU unprogrammed sequence to decrease the angles by one unit. The units of measurement are quoted as 40" of arc in Savage&Drake, but actually they were 39.55078125" of arc, making the full range come out to exactly 360 degrees. |
| 33 |
CDUY |
|
| 34 |
CDUZ |
|
| 35 |
OPTY |
These
counters are used to monitor the orientation of the optics subsystem
(i.e., the line of sight) or LM rendezvous radar with respect to the
spacecraft. Two Control Data Units (CDUs) are dedicated to
measuring these relative angles. OPTY refers to the trunnion
angle, whereas OPTX refers to the shaft angle. The CDUs are like
analog-to-digital converters, and convert the analog angles to digital
data comprehended by the CPU. These counters contain 15-bit 2's-complement unsigned values, and therefore can take values ranging from 0 to 32767 (decimal). The counters are processed with the PCDU unprogrammed sequence (see below) in order to increase the angles by one unit, and are processed with the MCDU unprogrammed sequence to decrease the angles by one unit. The units of measurement are quoted in Savage&Drake as 10" of arc for the optical trunnion angle, or 40" of arc for the radar trunnion angle or optical or radar shaft angles; but they were actually 9.887695312" and 39.55078125" of arc, respectively, making the full range come out to exactly 90 or 360 degrees. |
| 36 |
OPTX |
|
| 37 |
PIPAX |
"PIPA"
stands for "Pulsed Integrating Pendulous Accelerometer". There
are 3 PIPAs mounted on the stable platform of the Inertial Management
Unit (IMU). Since the PIPAs are "integrating", they measure
changes in velocity (i.e., "delta-V") rather than acceleration, and the
counters PIPAX, PIPAY, PIPAZ
thus monitor the velocity of the spacecraft (as long as gimbal lock has
not occurred). Savage&Drake quote the units as 5.85 cm./sec
or 1 cm./sec., but do not state the conditions under which the two
different units are used. I assume these counters are incremented or decremented with PINC or MINC unprogrammed sequences, but I haven't found any documentation for this conjecture yet. |
| 40 |
PIPAY |
|
| 41 |
PIPAZ |
|
| 42 |
Q-RHCCTR (RHCP) "Pitch" |
LM
only. Each of these registers holds a count in 1's-complement
format, indicating the
displacement of the rotational hand controller (RHC) in the pitch,
yaw, or roll axes.
The way this is supposed to work is as follows: There is a
deadband
near the detent, where the count is supposed to be zero. When
outside
of the deadband, the counter is supposed to continually update to
correspond to the angular displacement. The count begins to be
non-zero
after the angle has reached about 2°, is calibrated to a count of
42 at
10° (which is the nominal full-scale position), and increases until
reaching a mechanical stop at 13°. The counts are supposed to
update only if the RHC counts are enabled (bit 8 of output channel 013
set) and when the count is requested (bit 9 of output channel 013
set). In other words, the flight software must enable the
counters and then request new data whenever it wants new data.
Furthermore, the fact that the RHC is out of detent is reported to the
CPU by clearing bit 15 of channel 031 to zero. In practice, of course, people will be using 3D joysticks intended for games, rather than the actual LM RHC, so there's no way the yaACA program that manages all this can enforce these angles. So the way it actually works is this: yaACA assumes that the usable range in each axis, as reported by the joystick driver, is -127 to +127. (Any values outside this range are simply forced to be -127 or +127.) A raw value of 13 or less appears in the counter register as 0, a raw value of 97 appears in the counter register as 42, and all other values are scaled linearly from these reference points. The formula is Counter = (Raw - 13)/2. The maximum possible count is thus 57. For negative deflections, of course, the same formula applies but is simply negative. This formula is based partially on the characteristics of the LM RHC, but is also partially based on being able to translate from raw joystick values to RHCCTR registers relatively elegantly. It is, of course, possible to use MINC and PINC commands to alter the value of these register, but in the interest of reliablity, yaACA reports the count to yaAGC via fictitious input channels, 0170 (roll) or 0167 (yaw) or 0166 (pitch). The value in the input channel is a 1's-complement value in the range -57 to +57, and is placed directly in the counter by yaAGC. |
| 43 |
P-RHCCTR (RHCY) "Yaw" |
|
| 44 |
R-RHCCTR (RHCR) "Roll" |
|
| 45 |
INLINK |
This register is used to receive
digital uplink data from a ground station. After the incoming
data word is deposited in the register, the UPRUPT interrupt-request is
set. Correct data is in one of two forms: the value 0
(which the ground station may uplink for error-recovery purposes) or
the triply-redundant bit pattern cccccCCCCCccccc,
where CCCCC is meant to
be the logical complement of ccccc
, which is always a
DSKY-type keycode. Other patterns will be interpreted by the
flight software as corrupted data. |
| 46 |
RNRAD |
|
| 47 |
GYROCTR (GYROCMD) |
These registers are used during
IMU fine alignment to torque the gyro to the the precise alignment
expected by the AGS. (The tolerance of fine alignment is
approximately ±80" of arc.) This register is written
by the flight software with counts (in AGC
1's-complement format) that represent the desired drive on the
currently selected axis. Only one axis can be selected at any
given time---namely, +X, -X, +Y, -Y, +Z, or -Z---using bits 7-9 of
output channel 014. Each count represents ±0.617981" of
arc.
Actual torquing of the gyro does not begin until bit 10 of output
channel 014 is set. (For completeness, note also that bit 6 of
channel 014 is supposed to be set at least 20 ms. prior to any of the
other stuff just mentioned.) If the torque is supposed to be 1-16383 counts, it should be achieved in a single burst. However, if it is greater than that, it should be achieved by bursts of 8192 counts each, with bursts separated by 30 ms. If you examine the Luminary131 software, you'll see that it does exactly this. Upon detecting a non-zero value in the GYROCTR register while the gyro activity bit (10) in channel 014 is set, the true AGC would emit a stream of electronic pulses at a rate of 3200 pulses per second, with a pulse-count equal to the register value. yaAGC behaves simularly, except that it emits fictitious output channels 0174-0176, each one of which can contain multiple pulses, scheduled to roughly correspond to the 3200 pps. timing. As soon as yaAGC has read the GYROCTR register, it resets it to zero. I have no idea if the actual AGC did this or not. |
| 50 |
CDUXCMD |
These
registers are used during IMU coarse alignment to drive the IMU stable
platform to approximately the orientation expected by the AGC.
(The tolerance of coarse alignment is approximately
±1.5°.) These registers are written by the flight
software with counts (in AGC
1's-complement format) that represent the desired drive in each
axis. Each count represents ±0.04375°. (192
counts represent ±8.4 degrees.) The drive sequence does
not actually commence until the corresponding drive-enable bit is set
in output channel 14 (octal). Bit 15 (the most significant bit)
of channel 14 must be set to drive in the X axis, bit 14 in the Y axis,
and bit 13 in the Z axis. yaAGC
does not perform this operation instantly, but instead simulates the
true AGC timing (which emits a burst of 192 count-pulses every 600 ms.
when active), using the fictitious
output channel 0177. Notice that all three axes can be
slewed
simultaneously if multiple drive bits are set in channel 014. yaAGC zeroes the CDUxCMD registers as soon as it has read them while the corresponding drive-bit in channel 014 is set. I have no idea if the actual AGC behaved this way or not. |
| 51 |
CDUYCMD |
|
| 52 |
CDUZCMD |
|
| 53 |
OPTYCMD |
|
| 54 |
OPTXCMD |
|
| 55 |
THRUST |
LM only. |
| 56 |
LEMONM |
LM only. |
| 57 |
OUTLINK |
One might suppose that since the INLINK
register is used for digital uplinks, then the OUTLINK register is used
for digital downlinks. Actually, output channels 013, 034, and
034 are used for digital downlinks. I have no idea at all what
the OUTLINK register is used for, unless it is somehow used in the
downlink process, but not actually accessed by the flight software. |
| 60 |
ALTM |
LM only. |
| Vector
Address (octal) |
Interrupt
Name |
Trigger
Condition |
Description |
| 4000 |
(boot) |
Power-up
or GOJ signal. |
This is
where the program begins executing at power-up. |
| 4004 |
T6RUPT | Counter-register TIME6 decremented to 0. | The digital autopilot (DAP) for controlling thrust times of the jets of the reaction control system (RCS). |
| 4010 |
T5RUPT | Overflow
of counter-timer TIME5. |
Used by the autopilot. |
| 4014 |
T3RUPT | Overflow of counter-timer TIME3. | Used by the task scheduler (WAITLIST). |
| 4020 |
T4RUPT | Overflow of counter-timer TIME4. | Used for various DSKY-related activities such as monitoring the PRO key and updating display data. |
| 4024 |
KEYRUPT1 | Keystroke
received from DSKY. |
The DSKY
transmits codes representing keystrokes to the AGC. Reception of
these codes by the AGC hardware triggers an interrupt. |
| 4030 |
KEYRUPT2 | Keystroke received from secondary DSKY. |
In
the CM, there was a second DSKY at the navigator's station, used for
star-sighting data, in conjunction with the Alignment Optical Telescope
(AOT). There was no 2nd DSKY in the LM, but the interrupt was not
re-purposed. |
| 4034 |
UPRUPT | Uplink
word available in the INLINK register. |
Data
transmitted from ground-control for the purpose of controlling or
monitoring the AGC is in the form of a serial data stream which is
assembled in AGC INLINK counter-register. When a word has been
assembled in this fashion, an interrupt is triggered. |
| 4040 |
DOWNRUPT | The downlink shift register is
ready for new data (output channels 34 & 35). |
Used for
telemetry-downlink. |
| 4044 |
RADAR RUPT | Overflow in the counter-register RNRAD. | Data from the rendezvous radar is
apparently assembled similarly to the uplink data described
above. When a data word is complete, an interrupt is triggered. |
| 4050 |
RUPT10
(LM) |
TBD | Used for LM landing guidance, but details are TBD |
| HANDRUPT
(CM) |
TBD | Used for CM hand control, but details are TBD |
| Description: |
The "Add"
instruction adds the contents of a memory location into the accumulator. |
| Syntax: |
AD K |
| Operand: |
K is the label of a memory
location. It must assemble to a 12-bit memory address. |
| Extracode: | This is not an extracode, and therefore cannot be preceded by an EXTEND instruction. |
| Timing: |
2 MCT (about 23.4 µs) |
| Flags: |
The Overflow depends on the
result of the operation, and can be positive, negative, or none.
The Extracode flag remains clear. |
| Editing: |
Editing is done upon writing to K, if K is CYR, SR, CYL, or EDOP. |
| Octal: |
60000 + K |
| Notes: |
The
accumulator is not overflow-corrected prior to the addition. The contents of K are added to the
accumulator, which retains any overflow that resulted from the addition. A side-effect of this instruction is that K is rewritten after its value is written to the accumulator; this means that if K is CYR, SR, CYL, or EDOP, then it is re-edited. Note that the normal result of AGC arithmetic such as (+1)+(-1) is -0. For the special case "AD A", refer instead to the DOUBLE instruction. |
| Description: |
The "Add to Storage"
instruction adds the accumulator to an erasable-memory location (and
vice-versa). |
| Syntax: |
ADS K |
| Operand: |
K is the label of a memory
location. It must assemble to a 10-bit memory address in erasable
memory. |
| Extracode: | This is not an extracode, and therefore cannot be preceded by an EXTEND instruction. |
| Timing: |
2 MCT (about 23.4 µs) |
| Flags: |
The Overflow is set according to
the result of the addition.
The Extracode flag remains clear. |
| Editing: |
Editing is done upon writing to K, if K is CYR, SR, CYL, or EDOP. |
| Octal: |
26000 + K |
| Notes: |
The contents of the accumulator
and K are added together,
and the
result is stored both in the accumulator and in K. The accumulator is
neither overflow-corrected prior to the addition nor after it.
However, the sum is overflow-corrected prior to being saved at K if K is a 15-bit register.
If K is a 16-bit
register like L or Q, then the sum is not overflow corrected before
storage. Note that the normal result of AGC arithmetic such as (+1)+(-1) is -0. If the destination register is 16-bits (L or Q register), then the non-overflow-corrected values added. |
| Description: |
The "Augment"
instruction increments a positive value in an erasable-memory location
in-place by +1, or a negative value by -1. |
| Syntax: |
AUG K |
| Operand: |
K is the label of a memory
location. It must assemble to a 10-bit memory address in erasable
memory. |
| Extracode: | This is an extracode, and therefore must be preceded by an EXTEND instruction. |
| Timing: |
2 MCT (about 23.4 µs) |
| Flags: |
The Overflow is set according to
the result of the operation.
The Extracode flag is cleared. |
| Editing: |
Editing is done upon writing to K, if K is CYR, SR, CYL, or EDOP. |
| Octal: |
24000 + K |
| Notes: |
If K
is a 16-bit register like A, L, or Q, then arithmetic is performed on
the
full 15-bit value (plus sign). Otherwise, only the available
14-bit value (plus sign) is used. If the contents of K before the operation is greater than or equal to +0, it is incremented by +1. On the other hand, if it is less than or equal to -0, it is decremented. If K is one of the counter registers which triggers an interrupt upon overflow, then an oveflow caused by AUG will trigger the interrupt also. These registers include TIME3-TIME6. Furthermore, if K is the TIME1 counter and the AUG causes an overflow, the TIME2 counter will be incremented. Some of the counter registers such as CDUX-CDUZ are formatted in 2's-complement format, but the AUG instruction is insensitive to this distinction and always uses normal 1's-complement arithmetic. |
| Description: |
The "Branch Zero to Fixed"
instruction jumps to a memory location in fixed (as opposed to
erasable) memory if the accumulator is zero. |
| Syntax: |
BZF K |
| Operand: |
K is the label of a memory
location. It must assemble to a 12-bit memory address in fixed
memory. (In other words, the two most significant bits of address
K cannot be 00.) |
| Extracode: | This is an extracode, and therefore must be preceded by an EXTEND instruction. |
| Timing: |
1 MCT (about 11.7 µs) if the accumulator is plus zero or minus zero, or 2 MCT (about 23.4 µs) if the accumulator is non-zero. |
| Flags: |
The Overflow is not
affected. The Extracode flag is cleared. The Q register
is unaffected. |
| Editing: |
The CYR, SR, CYL, and EDOP registers are not affected. |
| Octal: |
10000 + K |
| Notes: |
If
the accumulator is
non-zero, then control proceeds to the next
instruction. Only if the accumulator
is plus zero or minus zero
does
the branch to address K
occur. The accumulator (and its stored overflow) are not actually
modified. Note that if the accumulator contains overflow, then the accumulator is not treated as being zero, even if the sign-corrected value would be +0 or -0. This instruction does not set up a later return. Use the TC instruction instead for that. Indirect conditional branch: For an indirect conditional branch, it is necessary to combine an INDEX instruction with a BZF instruction. Refer to the entry for the INDEX instruction. |
| Description: |
The "Branch Zero or Minus to
Fixed"
instruction jumps to a memory location in fixed (as opposed to
erasable) memory if the accumulator is zero or negative. |
| Syntax: |
BZMF K |
| Operand: |
K is the label of a memory
location. It must assemble to a 12-bit memory address in fixed
memory. (In other words, the two most significant bits of address
K cannot be 00.) |
| Extracode: | This is an extracode, and therefore must be preceded by an EXTEND instruction. |
| Timing: |
1 MCT (about 11.7 µs) if the accumulator is zero or negative, or 2 MCT (about 23.4 µs) if the accumulator is positive non-zero. |
| Flags: |
The Overflow is not
affected. The Extracode flag is cleared. The Q register
is unaffected. |
| Editing: |
The CYR, SR, CYL, and EDOP registers are not affected. |
| Octal: |
60000 + K |
| Notes: |
If the accumulator
is positive
non-zero, then control proceeds to the next instruction. Only if
the accumulator is plus
zero or negative does the branch to address K occur. The accumulator
and its stored oveflow are not actually modified. Note that if the accumulator contains +overflow, then the accumulator is not treated as being zero, even if the sign-corrected value would be +0. If the accumulator contains negative overflow, then the value is treated as being negative non-zero, so the jump is taken. This instruction does not set up a later return. Use the TC instruction instead for that. Indirect conditional branch: For an indirect conditional branch, it is necessary to combine an INDEX instruction with a BZMF instruction. Refer to the entry for the INDEX instruction. |
| Description: |
The "Clear and Add"
(or "Clear and Add Erasable" or "Clear and Add Fixed") instruction
moves the contents of a memory location into the accumulator. |
| Syntax: |
CA K or CAE K or CAF K |
| Operand: |
K is the label of a memory
location. It must assemble to a 12-bit memory address. The CAE or CAF variants differ from the
generic CA, only in that
the assembler is supposed to display error messages if K is not in erasable or fixed
memory, respectively. |
| Extracode: | This is not an extracode, and therefore cannot be preceded by an EXTEND instruction. |
| Timing: |
2 MCT (about 23.4 µs) |
| Flags: |
The Overflow is cleared, unless K is the accumulator or the Q
register.
The Extracode flag remains clear. |
| Editing: |
Editing is done upon writing to K, if K is CYR, SR, CYL, or EDOP. |
| Octal: |
30000 + K |
| Notes: |
A
side-effect of this instruction is that K is rewritten after its value
is written to the accumulator; this means that if K is CYR, SR, CYL, or EDOP,
then it is re-edited. Note that if the source register contains 16-bits (like the L or Q register), then all 16 bits will be transferred to the accumulator, and thus the overflow will be transferred into A. On the other hand, if the source register is 15 bits, then it will be sign-extended to 16 bits when placed in A. For the special case "CA A", refer instead to the NOOP instruction. |
| Description: |
The "Count, Compare, and Skip"
instruction stores a variable from erasable memory into the accumulator
(which is decremented), and then performs
one of several jumps based on the original value of the variable.
This is the only "compare" instruction in the AGC instruction set. |
| Syntax: |
CCS K |
| Operand: |
K is
the label of a memory location. It must assemble to a 10-bit
memory
address in erasable memory. |
| Extracode: | This is not an extracode, and therefore cannot be preceded by an EXTEND instruction. |
| Timing: |
2 MCT (about 23.4 µs) |
| Flags: |
The Overflow is set according to
the result of the operation. The Extracode flag remains
cleared. |
| Editing: |
The contents of K is edited if K is one of the special registers CYR, SR, CYL, or EDOP. |
| Octal: |
10000 + K |
| Notes: |
The operation of this
instruction is rather complex:
Note that the net effect of the way overflow is treated when K is A, L, or Q is to allow 15-bit loop counters rather than mere 14-bit loop counters. For example, if A contains +1 with +overflow, then CCS A will place +0 with +overflow into A, and another CCS A will place 037777 without overflow into A, and thus no anomaly is seen when decrementing from +overflow to no overflow. The overflow of the accumulator will generally be cleared by this operation except in the kinds of cases decribed in the preceding paragraph. |
| Description: |
The
"Complement the Contents of A" bitwise complements the accumulator |
| Syntax: |
COM |
| Operand: |
This instruction has no operand. |
| Extracode: | This is not an extracode, and therefore cannot be preceded by an EXTEND instruction. |
| Timing: |
2 MCT (about 23.4 µs). |
| Flags: |
The Overflow is unaffected.
The Extracode flag remains clear. |
| Editing: |
The editing registers CYR, SR,
CYL, or EDOP are unaffected. |
| Octal: |
40000 |
| Notes: |
All 16 bits of the accumulator
are complemented. Therefore, in addition to negating the contents
of the register (i.e., converting plus to minus and minus to plus), the
overflow is preserved. This instruction assembles as "CS A". |
| Description: |
The "Clear and Subtract"
instruction moves the 1's-complement (i.e., the negative) of a memory
location into the accumulator. |
| Syntax: |
CS K |
| Operand: |
K is the label of a memory
location. It must assemble to a 12-bit memory address. |
| Extracode: | This is not an extracode, and therefore cannot be preceded by an EXTEND instruction. |
| Timing: |
2 MCT (about 23.4 µs) |
| Flags: |
The Overflow is cleared, unless K is the accumulator.
The Extracode flag remains clear. |
| Editing: |
Editing is done upon writing to K, if K is CYR, SR, CYL, or EDOP. |
| Octal: |
40000 + K |
| Notes: |
A side-effect of this instruction is that K is rewritten with its original value after the accumulator is written; this |