The
Launch Vehicle Digital Computer (LVDC) was a computer that resided
in the Instrument Unit (IU) that perched above the Saturn IVB that
was the second stage in a Saturn IB rocket and the third stage in a
Saturn V rocket. The LVDC was a completely separate computer
system from the AGC, with a different architecture, different
instruction-set, and different runtime software. The purpose
of the LVDC was to precisely control the Saturn from shortly before
liftoff until the point at which the Saturn was discarded by the
CSM. |
Factoid
People generally think that the guidance computer (AGC) of
the command module controlled the Saturn rocket, but it
isn't true. During burns of the S-II and S-IVB rocket
stages, it was
possible for the CSM's AGC to control the steering, as a
backup to the LVDC. This was not possible during burns
of the first stage (S-IB or S-IC). On the CSM's
DSKY, the crew could see a display of various measurements
taken by the rocket's sensors. I don't think the
backup capability was ever used in a mission. Correct
me if I'm wrong, please! However, the AGC's ability to
directly control the Saturn IVB was used for other purposes
during the mission. Also, see below. |

![]() |
|
![]() |



The LVDC and the AGC did not actually have any direct
interaction, so we may as well talk about how the AGC
interacted with the Saturn before immersing ourselves in
too much detail about the LVDC.
If you look at
either of the graphics at the end of the preceding
section, you'll see the four ways that the Instrumentation
Unit (IU) in the Saturn IVB and the Spacecraft (i.e, the
Command Module) — which are separated by a horizontal
dotted line near the tops of the two graphics —
interacted:
However, it was also possible for the spacecraft to send
the flight control computer a signal, the Mode Command,
which instructed it to accept Alternate Steering Commands
from the AGC rather than the default steering commands
from the LVDC/LVDA. Thus, the AGC could steer the
Saturn IVB (but not some of the other Saturn stages) by
this mechanism.
Of course, it was also desirable for the spacecraft to be
able to monitor the activity of the Saturn, even under
normal conditions when the LVDC was controlling the
rocket. Since the spacecraft had its own Inertial
Measurement Unit (IMU), it knew its own orientation and
acceleration — and hence the Saturn's — at all times, and
the AGC could integrate these quantities to know the
velocity and position at all times. Thus it was not
necessary for the IU to communicate that information to
the spacecraft in order for the AGC to monitor the
physical motion of the rocket and to display it for the
astronauts on the DSKY.
I actually have an interesting graphic of the monitoring process to show you. Even though we do not have any of the original LVDC software at the present time, and thus cannot simulate the operation of the LVDC in a digital sense, a fellow named Riley Rainey has used the equations defining the IU to model the physical behavior of the rocket and the spacecraft's IMU, allowing Virtual AGC to monitor the launch behavior on a simulated DSKY. Here's a short movie he has created of that simulation. It's admittedly a little fuzzy, since I blew it up by about 2×, but perhaps we'll be able to get a better one sometime in the future:
However ... each of the flown Saturns is associated with a report
known as its "launch vehicle flight evaluation report", and these reports are available for most
of the missions, though there are a few gaps. Chapter
2 of each of the reports divides the mission into a set of "time
bases", called T0, T1, ..., T5, T5A,
T6, ..., T9, and each time base itself
consists of a series of events that are supposed to occur at
different times. For example, time base T0 is
always the "Guidance Reference Release", and comprises events such
as "S-IC Engine Start Sequence Command", "S-IC Engine No. 1
Start", and so on. But in general, not all missions use all
of the time bases, and the time bases aren't necessarily used for
the same thing on different missions.
By examining these time bases on a mission-by-mission basis, it's
possible to roughly deduce which missions may have flown with the
same LVDC software (though with differing preloaded constants) vs
the missions which must necessarily have used different LVDC
software. Thanks to Nik Beug for pointing this out.
While such an analysis has not been done comprehensively, a rough
analysis of the gross similarities in the time bases might
indicate the need for at least the following different LVDC
software versions:
Regarding preloaded constants for LVDC memory, all missions (I
think!) were associated with a report called the "launch vehicle
operational flight trajectory", and these documents (among other
things) listed the LVDC preload settings. Unfortunately,
most of these reports are presently unavailable, though we do have a
few of them. For example, the AS-202 report says that
"LVDC symbol" T1i, the time-to-go for first IGM stage,
is preloaded with 299.25 sec, while Vex1, the J2
exhaust velocity for first IGM stage, is loaded with 4165.45
m/sec, and so on.




|
|
Mnemonic |
A 8 |
A 9 |
O P 4 |
O P 3 |
O P 2 |
O P 1 |
Timing (computer cycles) |
Description of the instruction |
||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| HOP |
X |
X |
0 |
0 |
0 |
0 |
2 (?) |
This instruction combines an unconditional jump
instruction with various other configuration options, such
as memory-sector selection. The way it works is that
the address A1-A9 points to a memory word that contains a
"HOP constant", and the HOP instruction transfers
that HOP constant into the HOP register. Recall that
A1-A8 select the offset within a 256-word sector, and A9 is
the "residual bit" that selects between the current sector
and the "residual sector". There is no provision for a
partial HOP constant, and the full HOP constant needs to be
given every time a HOP instruction is
used. See also CDS and TRA. |
||||||||||||||||||||||||||||||||||||
| MPY |
X |
X |
0 |
0 |
0 |
1 |
1 (results available after 4) |
This is a multiplication instruction. It multiplies two 24-bit numbers to produce a 26-bit product. The accumulator provides the address of one operand, and the address embedded in the instruction points to the other operand. Recall that A1-A8 select the offset within a 256-word sector, and A9 is the "residual bit" that selects between the current sector and the "residual sector". In both cases, the most-significant 24-bits of the operands are used, and the least-significant 2 bits of the operand are ignored. A partial product (24 bits from the addressed memory times the 12 less-significant bits from the accumulator) can be fetched from the P-Q Register (0775 octal) on the 2nd instruction (or more accurately, two computer cycles) following MPY, though there is no need to do so if that value isn't desired by the program. The full product is available from the accumulator or from the P-Q Register on the 4th instruction (more accurately, 4 computer cycles) following MPY. However, the result will remain in the P-Q register until the next MPH, MPY, or DIV. | ||||||||||||||||||||||||||||||||||||
| SUB |
X |
X |
0 |
0 |
1 |
0 |
1 |
Subtracts the contents of a word pointed to by the address embedded within the instruction from the accumulator, and puts the result back into the accumulator. Recall that A1-A8 select the offset within a 256-word sector, and A9 is the "residual bit" that selects between the current sector and the "residual sector". See also RSU. | ||||||||||||||||||||||||||||||||||||
| DIV |
X |
X |
0 |
0 |
1 |
1 |
1 (results available after 8) |
This is the division instruction. The contents of the accumulator are divided by the operand pointed to by the address A1-A9 embedded within the instruction to produce a 24-bit quotient. Recall that A1-A8 select the offset within a 256-word sector, and A9 is the "residual bit" that selects between the current sector and the "residual sector". The quotient is available in the P-Q Register (0775 octal) on the 8th instruction (more accurately, 8 computer cycles) following the DIV. However, the result will remain in the P-Q register until the next MPH, MPY, or DIV. | ||||||||||||||||||||||||||||||||||||
| TNZ |
X |
X |
0 |
1 |
0 |
0 |
1 |
This is a conditional jump instruction, which branches to
the address embedded in the instruction if the accumulator
is not zero, but simply continues to the next instruction in
sequence if the accumulator is zero. Bits A1-A8 of the
embedded address represent the new offset within the
currently selected 256-word instruction sector, while bit A9
gives the syllable number within that word. The
"residual sector" cannot be accessed. See also TMI. |
||||||||||||||||||||||||||||||||||||
| MPH |
X |
X |
0 |
1 |
0 |
1 |
5 |
This is a multiplication instruction. It is exactly
like MPY except that the program
"holds" until the multiplication is complete, so that the
product is available from the accumulator or from the P-Q
Register at the next instruction following MPY.
However, the result will remain in the P-Q register until
the next MPH, MPY,
or DIV. |
||||||||||||||||||||||||||||||||||||
| AND |
X |
X |
0 |
1 |
1 |
0 |
1 |
Logically ANDs the contents of the accumulator with the contents of the address embedded within the instruction and places the result in the accumulator. Recall that A1-A8 select the offset within a 256-word sector, and A9 is the "residual bit" that selects between the current sector and the "residual sector". | ||||||||||||||||||||||||||||||||||||
| ADD |
X |
X |
0 |
1 |
1 |
1 |
1 |
Adds the contents of the accumulator with the contents of the address embedded within the instruction and places the result in the accumulator. Recall that A1-A8 select the offset within a 256-word sector, and A9 is the "residual bit" that selects between the current sector and the "residual sector". | ||||||||||||||||||||||||||||||||||||
| TRA |
X |
X |
1 |
0 |
0 |
0 |
1 |
This is an unconditional jump instruction, which branches to the address embedded in the instruction. Bits A1-A8 of the embedded address represent the new offset within the currently selected 256-word instruction sector, while bit A9 gives the syllable number within that word. The "residual sector" cannot be accessed. | ||||||||||||||||||||||||||||||||||||
| XOR |
X |
X |
1 |
0 |
0 |
1 |
1 |
Logically exclusive-ORs the contents of the accumulator with the contents of the address embedded within the instruction and places the result in the accumulator. Recall that A1-A8 select the offset within a 256-word sector, and A9 is the "residual bit" that selects between the current sector and the "residual sector". | ||||||||||||||||||||||||||||||||||||
| PIO |
X |
X |
1 |
0 |
1 |
0 |
1 |
Reads or writes an i/o
port. Bits A1-A9 select the source and
destination of the i/o. A table of the i/o ports
vs. addresses is given in the following section. |
||||||||||||||||||||||||||||||||||||
| STO |
X |
X |
1 |
0 |
1 |
1 |
1 |
Stores the contents of the
accumulator in the word indicated by the address embedded
within the instruction. Recall that A1-A8 select the
offset within a 256-word sector, and A9 is the "residual
bit" that selects between the current sector and the
"residual sector". The following addresses are
special:
|
||||||||||||||||||||||||||||||||||||
| TMI |
X |
X |
1 |
1 |
0 |
0 |
1 |
This is a conditional jump instruction, which branches to the address embedded in the instruction if the accumulator is less than zero, but simply continues to the next instruction in sequence if the accumulator greater than or equal to zero. Bits A1-A8 of the embedded address represent the new offset within the currently selected 256-word instruction sector, while bit A9 gives the syllable number within that word. The "residual sector" cannot be accessed. See also TNZ. | ||||||||||||||||||||||||||||||||||||
| RSU |
X |
X |
1 |
1 |
0 |
1 |
1 |
Same as SUB, except that the
order of the operands in the subtraction is reversed. |
||||||||||||||||||||||||||||||||||||
| CDS |
X |
0 |
1 |
1 |
1 |
0 |
1 |
Change the
currently-selected 256-word data sector. For this
instruction, A9 forms a part of the instruction itself, so
only A1-A8 are significant. The partially overwrite
the HOP Register as follows:![]() See also HOP. |
||||||||||||||||||||||||||||||||||||
| SHF |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
Performs a logical shift
operation on the accumulator. For this instruction,
bits A8 and A9 form a part of the instruction itself, but of
the remaining bits only A1, A2, A5, and A6 are actually
used, as follows:
|
||||||||||||||||||||||||||||||||||||
| EXM |
1 |
1 |
1 |
1 |
1 |
0 |
1 + cycles needed for target
instruction (?) |
"Execute modified".
This instruction takes an instruction stored at a specified
memory location, forms a modified A1-A9 field for that
instruction, executes that instruction, and then continues
with the next instruction following the EXM
(unless the program counter has been modified). For
this instruction, A8 and A9 form a part of the instruction
code, so only A1-A7 are significant. Only 4 different
target words are allowed, 0600, 0640, 0700, and 0740, and
they are all in the "residual sector". Many of the
bits in A1-A7 represent various types of modifications to
the embedded address at the target address rather than being
address bits themselves. Here are the
interpretations of bits A1-A7 in the EXM
instruction:
In baseball terms, this is the "infield fly rule" of the LVDC: it clearly does something, but it's hard to grasp exactly what it does. |
||||||||||||||||||||||||||||||||||||
| CLA |
X |
X |
1 |
1 |
1 |
1 |
1 |
Store a value to the accumulator, from the memory word at the address embedded within the instruction. Recall that A1-A8 select the offset within a 256-word sector, and A9 is the "residual bit" that selects between the current sector and the "residual sector". |
|
Address Field from PIO Instruction |
Data Source |
Data Destination |
Purpose
of the i/o port |
Comments |
||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| A9 |
A8 |
A7 |
A6 |
A5 |
A4 |
A3 |
A2 |
A1 |
||||
| X |
0 |
B |
B |
B |
B |
B |
0 |
X |
Accumulator Register |
Telemetry Register BBBBB
(?) |
For
all of these operations, it is also possible to use main
memory or residual memory as the Data Source. For main
memory, use A9,A8=0,1 and for residual memory use A9,A8=1,1. The selection of the specific address offset within memory of the Data Source word in this case is TBD. |
|
| X | 0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
Accumulator Register |
Mode Register |
||
| X | 0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
Accumulator Register | Discrete Output Register (Reset) |
||
| X | 0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
Accumulator Register | Discrete Output Register (Set) |
||
| X | 0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
Accumulator Register | Internal Control Register (Set) |
||
| X | 0 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
Accumulator Register | Internal Control Register (Reset) |
||
| X | 0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
Accumulator Register | Interrupt Register Reset |
||
| X | 0 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
Accumulator Register | Switch Selector Register (Load) |
This register is used by the the LVDC to issue commands to
specific vehicle devices such as the fuel valve
controls. The register has a 15-bit capacity. |
|
| X | 0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
Accumulator Register | Orbital Checkout |
||
| X | 0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
Accumulator Register | Switch Selector & Discrete Output Registers (Read) |
||
| X | 0 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
Accumulator Register | Switch Selector Interrupt Counter |
||
| X | 0 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
Accumulator Register | COD Error (Read) |
||
| X | 0 |
0 |
1 |
1 |
1 |
0 |
1 |
0 |
Accumulator Register | Interrupt Inhibit |
Interrupts can be programmatically masked or unmasked with PIO to Interrupt Inhibit. By setting a bit in Interrupt Inhibit corresponding to the interrupt whose masking is desired, that interrupt is thereby masked. Any combination of bits can be set, so any combination of interrupts can be masked. To reenable the interrupt, a 0 is written to the corresponding bit in Interrupt Inhibit. | |
| X | 0 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
Accumulator Register | Minor Loop Timed Interrupt Counter |
||
| X | 0 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
Accumulator Register | Ladder No. 1 |
||
| X | 0 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
Accumulator Register | Ladder No. 2 |
||
| X | 0 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
Accumulator Register | Ladder No. 3 |
||
| X | 0 |
1 |
1 |
1 |
0 |
0 |
1 |
0 |
Accumulator Register | Ladder No. 4 |
||
| X | 0 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
Accumulator Register | Ladder No. 5 |
||
| X |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
Error Monitor Register |
Accumulator Register | ||
| X |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
Command Receiver or RCA-110 |
Accumulator Register | ||
| X |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
Discrete Input Spares |
Accumulator Register | ||
| X |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
Telemetry Scanner |
Accumulator Register | ||
| X |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
Switch Selector |
Accumulator Register | ||
| X |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
Real Time |
Accumulator Register | ||
| X |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
Accelerometer Processor X |
Accumulator Register | ||
| X |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
Accelerometer Processor Z |
Accumulator Register | ||
| X |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
Accelerometer Processor Y |
Accumulator Register | ||
| X |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
Interrupt Storage |
Accumulator Register | ||
| X |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
Spare No. 6 |
Accumulator Register | ||
| X |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
Computer COD Counter Start |
Accumulator Register | ||
| X |
1 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
Fine Gimbal No. 1 |
Accumulator Register | ||
| X |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
Coarse Gimbal No. 3 |
Accumulator Register | ||
| X |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
Computer COD Counter Start |
Accumulator Register | ||
| X |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
Coarse Gimbal No. 1 |
Accumulator Register | ||
| X |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
Horizon Seeker No. 1 |
Accumulator Register | ||
| X |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
Spare No. 3 |
Accumulator Register | ||
| X |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
Spare No. 4 |
Accumulator Register | ||
| X |
1 |
1 |
0 |
0 |
1 |
0 |
1 |
1 |
Fine Gimbal No. 4 |
Accumulator Register | ||
| X |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
Spare No. 1 |
Accumulator Register | ||
| X |
1 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
Horizon Seeker No. 3 |
Accumulator Register | ||
| X |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
Horizon Seeker No. 2 |
Accumulator Register | ||
| X |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
Coarse Gimbal No. 4 |
Accumulator Register | ||
| X |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
Spare No. 5 |
Accumulator Register | ||
| X |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
Coarse Gimbal No. 2 |
Accumulator Register | ||
| X |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
Fine Gimbal No. 3 |
Accumulator Register | ||
| X |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
Spare No. 2 |
Accumulator Register | ||
| X |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
Fine Gimbal No. 2 |
Accumulator Register | ||
| X |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
Horizon Seeker No. 4 |
Accumulator Register | ||
| LVDC Data
Word Bit Position |
Description of function in
Saturn IB |
Description of function in
Saturn V |
Are these actually the
same thing? |
Comments |
|---|---|---|---|---|
| 11 |
RCA-110A interrupt |
Command LVDA/RCA-110A interrupt |
Probably. |
The RCA-110A is the ground-control computer. This interrupt implies that a command word has been received via digital uplink and is ready to be processed. See section 6.2.3 of Astrionic System Handbook, Saturn Launch Vehicles. |
| 10 |
S-IB low-level sensors dry "A" |
S-IC inboard engine out "A" |
If interpreted as "first stage engine out", yes. | |
| 9 |
RCA-110A interrupt |
Program re-cycle (RCA-110A) interrupt |
Probably. |
The RCA-110A is the ground-control computer. The
following is partly speculation, so take it with a grain of
salt: I believe that this interrupt may occur when a special
uplink command ("Terminate") is received. The purpose
of the "Terminate" command is to halt an operation from a
previously uplinked command (see the 2nd line above) and to
return the LVDC flight program to normal operation.
Since the "command LVDA/RCA-110A" interrupt would be
disabled until that processing is completed, a separate
interrupt for the "Terminate" command is needed, and that is
the "Program re-cycle" interrupt. |
| 8 |
S-IVB engine out "B" |
S-IVB engine out "B" |
Yes. |
|
| 7 |
S-IB outboard engines cutoff "A" |
S-IC propellant depletion/engine cutoff "A" |
If interpreted as "first stage engine cutoff", yes. | |
| 6 |
Manual initiation of S-IVB engine cutoff "A" |
S-II propellant depletion/engine cutoff |
Both refer to the second
stage, but ... don't know! |
|
| 5 |
Guidance reference release |
Guidance reference release |
Yes. |
|
| 4 |
Command decoder interrupt "A" or "B" |
Command receiver interrupt |
Probably. |
I think this
interrupt comes from the decoder that interprets uplinked
data (see the two RCA-110A interrupts above), but it's
unclear to me what the purpose is, or how "A" and "B"
differ. |
| 3 |
Simultanous memory error |
Temporary loss of control |
Yes. |
"Simultaneous memory error" refers to simultaneous parity
errors in a single address mirrored in duplexed memory
modules. This is also known by the acronym TLC, and
thus is obviously the same as "temporary loss of control". |
| 2 |
Spare |
Computer interface unit interrupt |
No. |
|
| 1 |
Internal to the LVDC |
Switch selector interrupt |
Probably. |
The switch-selector interrupt and
the minor-loop interrupt are
generated internally by the LVDC/LVDA. |
| S |
Internal to the LVDC |
Minor loop interrupt |
| "Forbidden Planet"
is really about the mysterious Krel, who were so advanced
technologically they were able to gain control over the
very essence of their material bodies. The mystery of why
they left no record of their physical appearance only
makes the irony of their destruction by the evil of "The
Mindless Primitive" within even more interesting. —G. D. Garduno
(2007), on the movie Forbidden Planet
|
| This web page is
about the mysterious LVDC, which was so advanced
technologically that it could guide the hurtling of a
montrously large rocket toward the moon. The mystery of
why no record was left of the computer software or even of
its visual appearance only makes the irony of its
destruction by the evil of "The Mindless Budget-Cutters"
even more interesting. —Ron Burkey (2009),
on LVDC assembly language
|
| # Sum of two double-precision
vectors A and B to produce vector C. CLA A ADD B STO C CLA A + 1 ADD B + 1 STO C + 1 CLA A + 2 ADD B + 2 STO C + 2 ... # Purportedly, subroutine linkages to call functions to perform vector addition. CLA ADRESA STO VCAADR CLA * + 2 HOP VCALINK HOPCON * + 1 CLA ADRESB STO VADADR CLA * + 2 HOP VADLINK HOPCON * + 1 CLA CADRES STO VTSADR CLA * + 2 HOP VTSLINK HOPCON * + 1 ... # Integration during accelerated flight. If you want to see the equations being # implemented, look at page 7 of the critique. AVERAGEG STO EXITHOP HOP HOPSET1 AVG1 CLA WK SHF R1 ADD HGK/2 ADD VK MPH H ADD R STO R MPY R HOP THISEC1 AVG4 CLA HOPWD1 ADD ONE STO HOPWD1 CLA PQ ADD DOTSUM STO DOTSUM HOPWD1 HOP HOPSET1 AVG2 CLA DOTSUM STO SQRTARG CLA * + 2 HOP SQRTLINK HOPCON * + 1 CLA SQRTANS MPY DOTSUM CLA -MUH/2 NOOP NOOP DIV PQ HOP THISSEC2 AVG5 CLA HOPSET1 STO HOPWD1 CLA HOPSET2 STO HOPWD2 NOOP NOOP NOOP CLA PQ STO DOTSUM HOP HOPSET2 AVG3 CLA R MPY DOTSUM CLA HGK/2 ADD W ADD V STO V CLA PQ STO HGK/2 ADD V STO V HOP THISSEC3 AVG6 CLA HOPWD2 ADD ONE STO HOPWD2 HOP HOPSET2 HOPSET1 HOPCON AVG1, XCOMP HOPCON AVG1, YCOMP HOPCON AVG1, ZCOMP HOPCON AVG2, XCOMP HOPSET2 HOPCON AVG3, YCOMP HOPCON AVG3, ZCOMP EXITHOP ( exit hop con ) STRTLINK HOPCON SQRT, XCOMP THISSEC1 HOPCON AVG4, AVG4 THISSEC2 HOPCON AVG5, AVG5 THISSEC3 HOPCON AVG6, AVG6 # Compute a double-precision square root. SQRT STO RETURN CLA ZERO STO NORMCNT CLA ARG NORMTEST AND HIGH3 TNZ NORMDUN CLA NORMCNT ADD ONE STO NORMCNT CLA ARG SHF L2 STO ARG TRA NORMTEST HIGH3 DEC -.75 1/2 DEC .5 SLOPELO DEC .4162 BIASLO DEC .1487 SLOPEHI DEC .2942 BIASHI DEC .2046 NORMDUN AND 1/2 TNZ ARGHI CLA ARG MPY SLOPELO SHF R1 STO ARG CLA BIASLO ADD PQ TRA NEWTON ARGHI CLA ARG MPY SLOPEHI SHF R1 STO ARG CLA BIASHI ADD PQ NEWTON STO BUF CLA ARG DIV BUF ADD ZERO ADD ZERO ADD ZERO ADD ZERO ADD ZERO ADD ZERO ADD ZERO CLA PQ SHF R1 ADD BUF STO BUF CLA ARG DIV BUF ADD ZERO ADD ZERO ADD ZERO ADD ZERO ADD ZERO ADD ZERO ADD ZERO CLA BUF SHF R1 ADD PQ STO ARG CLANORC CLA NORMCNT TNZ POSTSQRT CLA ARG SHF R1 STO ARG TRA CLANORC # Calling sequence for SQRT (or similar for any other unary subroutine). CLA X STO ARG CLA REHOP HOP SQRTLINK RETURN CLA ARG ... REHOP HOPCON RETURN SQRTLINK HOPCON SQRT |

